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Implements RTI, corrects TAY.
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0418f51ef2
commit
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@ -467,7 +467,7 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
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break;
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break;
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case TAY:
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case TAY:
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LD(x_, a_.full, x_masks_);
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LD(y_, a_.full, x_masks_);
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flags_.set_nz(y_.full, x_shift_);
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flags_.set_nz(y_.full, x_shift_);
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break;
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break;
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@ -483,7 +483,7 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
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//
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//
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// Jumps.
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// Jumps and returns.
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//
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//
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case JML:
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case JML:
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@ -513,6 +513,16 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
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pc_ = instruction_buffer_.value;
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pc_ = instruction_buffer_.value;
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break;
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break;
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case RTI:
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pc_ = uint16_t(data_buffer_.value >> 8);
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flags_.set(uint8_t(data_buffer_.value));
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if(!emulation_flag_) {
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program_bank_ = (data_buffer_.value & 0xff000000) >> 8;
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assert(false); // Extra flags to unpack!
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}
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break;
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//
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//
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// Block moves.
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// Block moves.
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//
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//
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@ -729,7 +739,7 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
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// REP, SEP,
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// REP, SEP,
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// XCE, XBA,
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// XCE, XBA,
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// STP, WAI,
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// STP, WAI,
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// RTI, RTL,
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// RTL,
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// TCD, TCS, TDC, TSC
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// TCD, TCS, TDC, TSC
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default:
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default:
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@ -649,6 +649,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CyclePull); // New PCL
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target(CyclePull); // New PCL
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target(CyclePull); // New PCH
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target(CyclePull); // New PCH
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if(!is8bit) target(CyclePull); // PBR
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if(!is8bit) target(CyclePull); // PBR
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// TODO: 8bit check here doesn't actually work, it needs to be an is-emulation-mode check.
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// New operation needed, I think.
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target(OperationPerform); // [RTI] — to unpack the fields above.
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target(OperationPerform); // [RTI] — to unpack the fields above.
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}
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}
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