diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index f3cde1803..5edd529df 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -39,6 +39,29 @@ ProcessorStorage::ProcessorStorage() {
 			OperationMoveToNextProgram
 		});
 
+	// 1b. Absolute a, JMP.
+	const auto absolute_jmp =
+		install_ops({
+			CycleFetchIncrementPC,			// OpCode.
+			CycleFetchIncrementPC,			// New PCL.
+			CycleFetchIncrementPC,			// New PCH.
+			OperationPerform,				// [JMP]
+			OperationMoveToNextProgram
+		});
+
+	// 1c. Absolute a, JSR.
+	const auto absolute_jsr =
+		install_ops({
+			CycleFetchIncrementPC,			// OpCode.
+			CycleFetchIncrementPC,			// New PCL.
+			CycleFetchIncrementPC,			// New PCH.
+			CycleFetchPreviousPC,			// IO.
+			OperationPerform,				// [JSR]
+			CyclePush,						// PCH
+			CyclePush,						// PCL
+			OperationMoveToNextProgram
+		});
+
 	// Install the instructions.
 #define op set_instruction
 	/* 0x00 BRK s */
@@ -75,7 +98,7 @@ ProcessorStorage::ProcessorStorage() {
 	/* 0x1e ASL a, x */
 	/* 0x1f ORA al, x */
 
-	/* 0x20 JSR a */
+	/* 0x20 JSR a */			op(0x20, absolute_jsr, JSR);
 	/* 0x21 ORA (d), y */
 	/* 0x22 AND (d, x) */
 	/* 0x23 JSL al */
@@ -121,7 +144,7 @@ ProcessorStorage::ProcessorStorage() {
 	/* 0x49	EOR # */
 	/* 0x4a	LSR A */
 	/* 0x4b	PHK s */
-	/* 0x4c	JMP a */
+	/* 0x4c	JMP a */			op(0x4c, absolute_jmp, JMP);
 	/* 0x4d	EOR a */			op(0x4d, absolute_read, EOR);
 	/* 0x4e	LSR a */
 	/* 0x4f	EOR Al */
diff --git a/Processors/65816/Implementation/65816Storage.hpp b/Processors/65816/Implementation/65816Storage.hpp
index 8ecef7ae6..53f767e51 100644
--- a/Processors/65816/Implementation/65816Storage.hpp
+++ b/Processors/65816/Implementation/65816Storage.hpp
@@ -16,11 +16,17 @@ class ProcessorStorage {
 		enum MicroOp: uint8_t {
 			/// Fetches a byte from the program counter to the instruction buffer and increments the program counter.
 			CycleFetchIncrementPC,
+			/// Does a no-effect fetch from PC-1.
+			CycleFetchPreviousPC,
+
 			/// Fetches a byte from the data address to the data buffer and increments the data address.
 			CycleFetchIncrementData,
 			/// Stores a byte to the data address from the data buffer and increments the data address.
 			CycleStoreIncrementData,
 
+			/// Pushes a single byte from the data buffer to the stack.
+			CyclePush,
+
 			/// Skips the next micro-op if in emulation mode.
 			OperationSkipIf8,
 
@@ -35,9 +41,21 @@ class ProcessorStorage {
 		};
 
 		enum Operation: uint8_t {
-			ADC, AND, BIT, CMP, CPX, CPY, EOR, LDA, LDX, LDY, ORA, SBC,
+			// These perform the named operation using the value in the data buffer.
+			ADC, AND, BIT, CMP, CPX, CPY, EOR, ORA, SBC,
 
+			// These load the respective register from the data buffer.
+			LDA, LDX, LDY,
+
+			// These move the respective register (or value) to the data buffer.
 			STA, STX, STY, STZ,
+
+			/// Loads the PC with the operand from the instruction buffer.
+			JMP,
+
+			/// Loads the PC with the operand from the instruction buffer, placing
+			/// the old PC into the data buffer.
+			JSR,
 		};
 
 		struct Instruction {