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https://github.com/TomHarte/CLK.git
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Provides feedback on interrupt flags, starts on state machine.
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@ -8,6 +8,8 @@
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#include "Audio.hpp"
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#include "Flags.hpp"
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#define LOG_PREFIX "[Audio] "
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#include "../../Outputs/Log.hpp"
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@ -61,10 +63,31 @@ void Audio::set_channel_enables(uint16_t enables) {
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void Audio::set_modulation_flags(uint16_t) {
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}
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void Audio::set_interrupt_requests(uint16_t requests) {
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channels_[0].interrupt_pending = requests & uint16_t(InterruptFlag::AudioChannel0);
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channels_[1].interrupt_pending = requests & uint16_t(InterruptFlag::AudioChannel1);
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channels_[2].interrupt_pending = requests & uint16_t(InterruptFlag::AudioChannel2);
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channels_[3].interrupt_pending = requests & uint16_t(InterruptFlag::AudioChannel3);
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}
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void Audio::run_for([[maybe_unused]] Cycles duration) {
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// TODO:
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//
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// Check whether any channel's period counter is exhausted and, if
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// so, attempt to consume another sample. If there are no more samples
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// and length is 0, trigger an interrupt.
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using State = Channel::State;
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for(int c = 0; c < 4; c++) {
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switch(channels_[c].state) {
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case State::Disabled:
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if(channels_[c].has_data && !channels_[c].dma_enabled && !channels_[c].interrupt_pending) {
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channels_[c].state = Channel::State::PlayingHigh;
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// TODO: [volcntrld, percntrld, pbufldl, AUDxID]
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}
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break;
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default: break;
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}
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}
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}
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@ -53,6 +53,9 @@ class Audio: public DMADevice<4> {
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/// their neighbours.
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void set_modulation_flags(uint16_t);
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/// Sets which interrupt requests are currently active.
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void set_interrupt_requests(uint16_t);
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private:
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struct Channel {
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// The data latch plus a count of unused samples
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@ -74,6 +77,9 @@ class Audio: public DMADevice<4> {
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// Indicates whether DMA is enabled for this channel.
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bool dma_enabled = false;
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// Records whether this audio interrupt is pending.
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bool interrupt_pending = false;
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// Replicates the Hardware Reference Manual state machine;
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// comments indicate which of the documented states each
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// label refers to.
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@ -83,7 +89,7 @@ class Audio: public DMADevice<4> {
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WaitingForDMA, // 101
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PlayingHigh, // 010
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PlayingLow, // 011
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} state_;
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} state = State::Disabled;
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} channels_[4];
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};
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@ -750,6 +750,7 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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case Write(0x09c): // INTREQ
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ApplySetClear(interrupt_requests_, 0x7fff);
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update_interrupts();
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audio_->set_interrupt_requests(interrupt_requests_);
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break;
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case Read(0x01e): // INTREQR
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cycle.set_value16(interrupt_requests_);
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