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https://github.com/TomHarte/CLK.git
synced 2025-01-11 08:30:55 +00:00
This might very well be the 68000's first real gasp: performing an ABCD.
This commit is contained in:
parent
bb04981280
commit
f9101de956
@ -616,6 +616,7 @@
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4BCF1FA41DADC3DD0039D2E7 /* Oric.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BCF1FA21DADC3DD0039D2E7 /* Oric.cpp */; };
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4BD388882239E198002D14B5 /* 68000Tests.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4BD388872239E198002D14B5 /* 68000Tests.mm */; };
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@ -1375,6 +1376,7 @@
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4BD3A3091EE755C800B5B501 /* Video.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = Video.cpp; path = ZX8081/Video.cpp; sourceTree = "<group>"; };
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@ -2822,6 +2824,7 @@
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4BB73EB51B587A5100552FC2 /* Clock SignalTests */ = {
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isa = PBXGroup;
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children = (
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4BD388872239E198002D14B5 /* 68000Tests.mm */,
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4B924E981E74D22700B76AF1 /* AtariStaticAnalyserTests.mm */,
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4BB2A9AE1E13367E001A5C23 /* CRCTests.mm */,
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4BFF1D3C2235C3C100838EA1 /* EmuTOSTests.mm */,
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@ -4024,6 +4027,7 @@
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4BB73EB71B587A5100552FC2 /* AllSuiteATests.swift in Sources */,
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4B01A6881F22F0DB001FD6E3 /* Z80MemptrTests.swift in Sources */,
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4B121F9B1E06293F00BFDA12 /* PCMSegmentEventSourceTests.mm in Sources */,
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4BD388882239E198002D14B5 /* 68000Tests.mm in Sources */,
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4BA91E1D216D85BA00F79557 /* MasterSystemVDPTests.mm in Sources */,
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4B98A0611FFADCDE00ADF63B /* MSXStaticAnalyserTests.mm in Sources */,
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4BEF6AAC1D35D1C400E73575 /* DPLLTests.swift in Sources */,
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87
OSBindings/Mac/Clock SignalTests/68000Tests.mm
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87
OSBindings/Mac/Clock SignalTests/68000Tests.mm
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@ -0,0 +1,87 @@
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//
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// 68000Tests.m
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// Clock SignalTests
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//
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// Created by Thomas Harte on 13/03/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#import <XCTest/XCTest.h>
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#include <array>
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#include <cassert>
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#include "68000.hpp"
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/*!
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Provides a 68000 with 64kb of RAM in its low address space;
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/RESET will put the supervisor stack pointer at 0xFFFF and
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begin execution at 0x0400.
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*/
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class RAM68000: public CPU::MC68000::BusHandler {
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public:
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RAM68000() : m68000_(*this) {
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ram_.resize(32768);
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// Setup the /RESET vector.
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ram_[0] = 0;
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ram_[1] = 0xffff;
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ram_[2] = 0;
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ram_[3] = 0x0400;
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}
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void set_program(const std::vector<uint16_t> &program) {
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memcpy(&ram_[512], program.data(), program.size() * sizeof(uint16_t));
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}
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void run_for(HalfCycles cycles) {
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m68000_.run_for(cycles);
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}
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HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int is_supervisor) {
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uint32_t address = cycle.address ? (*cycle.address) & 0x00fffffe : 0;
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switch(cycle.operation & (CPU::MC68000::Microcycle::LowerData | CPU::MC68000::Microcycle::UpperData)) {
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case 0: break;
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case CPU::MC68000::Microcycle::LowerData:
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cycle.value->halves.low = ram_[address >> 1] >> 8;
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break;
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case CPU::MC68000::Microcycle::UpperData:
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cycle.value->halves.high = ram_[address >> 1] & 0xff;
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break;
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case CPU::MC68000::Microcycle::UpperData | CPU::MC68000::Microcycle::LowerData:
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cycle.value->full = ram_[address >> 1];
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break;
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}
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return HalfCycles(0);
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}
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private:
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CPU::MC68000::Processor<RAM68000, true> m68000_;
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std::vector<uint16_t> ram_;
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};
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@interface M68000Tests : XCTestCase
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@end
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@implementation M68000Tests {
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std::unique_ptr<RAM68000> _machine;
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}
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- (void)setUp {
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_machine.reset(new RAM68000());
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}
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- (void)tearDown {
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_machine.reset();
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}
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- (void)testABCD {
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_machine->set_program({
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0xc100 // ABCD D0, D0
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});
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_machine->run_for(HalfCycles(400));
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}
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@end
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@ -15,12 +15,36 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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// for interrupts).
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if(active_step_->action == BusStep::Action::ScheduleNextProgram) {
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if(active_micro_op_) {
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++active_micro_op_;
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switch(active_micro_op_->action) {
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case MicroOp::Action::None: break;
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case MicroOp::Action::PerformOperation:
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std::cerr << "Should do something with program operation " << int(active_program_->operation) << std::endl;
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switch(active_program_->operation) {
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case Operation::ABCD: {
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// Pull out the two halves, for simplicity.
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const uint8_t source = active_program_->source->halves.low.halves.low;
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const uint8_t destination = active_program_->destination->halves.low.halves.low;
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// Perform the BCD add by evaluating the two nibbles separately.
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int result = (source & 0xf) + (destination & 0xf) + (extend_flag_ ? 1 : 0);
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if(result > 0x9) result += 0x06;
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result += (source & 0xf0) + (destination & 0xf0);
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if(result > 0x90) result += 0x60;
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// Set all flags essentially as if this were normal addition.
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zero_flag_ |= result & 0xff;
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extend_flag_ = carry_flag_ = result & ~0xff;
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negative_flag_ = result & 0x80;
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overflow_flag_ = ~(source ^ destination) & (source ^ result) & 0x80;
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// Store the result.
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active_program_->destination->halves.low.halves.low = uint8_t(result);
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} break;
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default:
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std::cerr << "Should do something with program operation " << int(active_program_->operation) << std::endl;
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break;
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}
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break;
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case MicroOp::Action::PredecrementSourceAndDestination1:
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@ -28,22 +52,33 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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-- active_program_->destination->full;
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break;
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case MicroOp::Action::PredecrementSourceAndDestination1:
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case MicroOp::Action::PredecrementSourceAndDestination2:
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active_program_->source->full -= 2;
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active_program_->destination->full -= 2;
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break;
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case MicroOp::Action::PredecrementSourceAndDestination1:
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case MicroOp::Action::PredecrementSourceAndDestination4:
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active_program_->source->full -= 4;
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active_program_->destination->full -= 4;
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break;
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}
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}
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if(active_micro_op_) {
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++active_micro_op_;
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active_step_ = active_micro_op_->bus_program;
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}
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if(!active_step_) {
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std::cerr << "68000 Abilities exhausted; should schedule an instruction or something?" << std::endl;
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return;
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if(!active_step_ || !active_micro_op_) {
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const uint16_t next_instruction = prefetch_queue_[0].full;
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if(!instructions[next_instruction].micro_operations) {
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std::cerr << "68000 Abilities exhausted; should schedule an instruction or something?" << std::endl;
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return;
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}
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active_program_ = &instructions[next_instruction];
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active_micro_op_ = active_program_->micro_operations;
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active_step_ = active_micro_op_->bus_program;
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}
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}
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std::vector<size_t> micro_op_pointers(65536, std::numeric_limits<size_t>::max());
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// Perform a linear search of the mappings above for this instruction.
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for(size_t instruction = 0; instruction < 65536; ++instruction) {
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for(size_t instruction = 0; instruction < 65536; ++instruction) {
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for(const auto &mapping: mappings) {
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if((instruction & mapping.mask) == mapping.value) {
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// Install the operation and make a note of where micro-ops begin.
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@ -228,11 +228,9 @@ void ProcessorStorage::install_instructions(const BusStepCollection &bus_step_co
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switch(mapping.decoder) {
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case Decoder::Decimal: {
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const int destination = (instruction >> 8) & 7;
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const int destination = (instruction >> 9) & 7;
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const int source = instruction & 7;
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all_micro_ops_.emplace_back();
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if(instruction & 8) {
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// Install source and destination.
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instructions[instruction].source = &bus_data_[0];
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// Various status bits.
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int is_supervisor_;
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int zero_flag_; // The zero flag is set if this value is zero.
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int carry_flag_; // The carry flag is set if this value is non-zero.
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int extend_flag_; // The extend flag is set if this value is non-zero.
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int overflow_flag_; // The overflow flag is set if this value is non-zero.
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int negative_flag_; // The negative flag is set if this value is non-zero.
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// Generic sources and targets for memory operations.
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uint32_t effective_address_;
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@ -88,8 +93,8 @@ class ProcessorStorage {
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*/
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struct Program {
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MicroOp *micro_operations = nullptr;
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RegisterPair32 *source;
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RegisterPair32 *destination;
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RegisterPair32 *source = nullptr;
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RegisterPair32 *destination = nullptr;
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Operation operation;
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};
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