From fafd1801fec7b64a892ec2f2626ee112271bc565 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Thu, 20 Jun 2019 19:02:03 -0400
Subject: [PATCH] Introduces first DIVS test, and associated fixes.

---
 .../Mac/Clock SignalTests/68000Tests.mm       | 27 ++++++++++++++++++-
 .../Implementation/68000Implementation.hpp    |  9 +++++--
 2 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/OSBindings/Mac/Clock SignalTests/68000Tests.mm b/OSBindings/Mac/Clock SignalTests/68000Tests.mm
index d7dc28113..10efe960b 100644
--- a/OSBindings/Mac/Clock SignalTests/68000Tests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000Tests.mm	
@@ -58,6 +58,7 @@ class RAM68000: public CPU::MC68000::BusHandler {
 
 		HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int is_supervisor) {
 			const uint32_t word_address = cycle.word_address();
+			duration_ += cycle.length;
 
 			using Microcycle = CPU::MC68000::Microcycle;
 			if(cycle.data_select_active()) {
@@ -101,10 +102,15 @@ class RAM68000: public CPU::MC68000::BusHandler {
 			return m68000_;
 		}
 
+		int get_cycle_count() {
+			return 0;
+		}
+
 	private:
 		CPU::MC68000::Processor<RAM68000, true, true> m68000_;
 		std::vector<uint16_t> ram_;
 		int instructions_remaining_;
+		HalfCycles duration_;
 };
 
 class CPU::MC68000::ProcessorStorageTests {
@@ -1038,7 +1044,26 @@ class CPU::MC68000::ProcessorStorageTests {
 	[self performDBccTestOpcode:0x5fca status:Flag::Negative | Flag::Overflow d2Outcome:0];
 }
 
-/* Further DBF tests omitted. */
+/* Further DBF tests omitted; they seemed to be duplicative, assuming I'm not suffering a failure of comprehension. */
+
+// MARK: DIVS
+
+- (void)testDIVSOverflow {
+	_machine->set_program({
+		0x83fc, 0x0001		// DIVS #1, D1
+	});
+	auto state = _machine->get_processor_state();
+	state.data[1] = 0x4768f231;
+	state.status = Flag::ConditionCodes;
+
+	_machine->set_processor_state(state);
+	_machine->run_for_instructions(2);
+
+	state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[1], 0x4768f231);
+	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow);
+	// Test: 20 cycles passed.
+}
 
 // MARK: MOVE USP
 
diff --git a/Processors/68000/Implementation/68000Implementation.hpp b/Processors/68000/Implementation/68000Implementation.hpp
index 929297743..0bec33d9f 100644
--- a/Processors/68000/Implementation/68000Implementation.hpp
+++ b/Processors/68000/Implementation/68000Implementation.hpp
@@ -1022,16 +1022,21 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
 										cycles_expended += 2;	// An additional microycle applies if the dividend is negative.
 									}
 
+									carry_flag_ = 0;
+
+									// These are officially undefined for results that overflow, so the below is a guess.
+									zero_result_ = decltype(zero_result_)(quotient & 0xffff);
+									negative_flag_ = zero_result_ & 0x8000;
+
 									// Check for overflow. If it exists, work here is already done.
 									if(quotient > 32767 || quotient < -32768) {
 										overflow_flag_ = 1;
 										active_step_->microcycle.length = HalfCycles(3*2*2);
+
 										break;
 									}
 
 									overflow_flag_ = 0;
-									zero_result_ = decltype(zero_result_)(quotient);
-									negative_flag_ = zero_result_ & 0x8000;
 
 									// TODO: check sign rules here; am I necessarily giving the remainder the correct sign?
 									// (and, if not, am I counting it in the correct direction?)