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https://github.com/TomHarte/CLK.git
synced 2024-12-25 03:32:01 +00:00
Expanded 6532 tests substantially, beefing up implementation to match.
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@ -38,10 +38,12 @@ template <class T> class MOS6532 {
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case 0x00: case 0x02:
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_port[decodedAddress / 2].output = value;
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static_cast<T *>(this)->set_port_output(decodedAddress / 2, _port[decodedAddress/2].output, _port[decodedAddress / 2].output_mask);
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set_port_did_change(decodedAddress / 2);
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break;
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case 0x01: case 0x03:
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_port[decodedAddress / 2].output_mask = value;
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static_cast<T *>(this)->set_port_output(decodedAddress / 2, _port[decodedAddress/2].output, _port[decodedAddress / 2].output_mask);
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set_port_did_change(decodedAddress / 2);
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break;
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// The timer and edge detect control
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@ -125,7 +127,10 @@ template <class T> class MOS6532 {
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}
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MOS6532() :
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_interrupt_status(0), _port{{.output_mask = 0, .output = 0}, {.output_mask = 0, .output = 0}}, _a7_interrupt({.last_port_value = 0, .enabled = false})
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_interrupt_status(0),
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_port{{.output_mask = 0, .output = 0}, {.output_mask = 0, .output = 0}},
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_a7_interrupt({.last_port_value = 0, .enabled = false}),
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_interrupt_line(false)
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{}
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inline void set_port_did_change(int port)
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@ -149,6 +154,11 @@ template <class T> class MOS6532 {
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}
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}
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inline bool get_inerrupt_line()
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{
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return _interrupt_line;
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}
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private:
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uint8_t _ram[128];
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@ -173,6 +183,7 @@ template <class T> class MOS6532 {
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Timer = 0x80,
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PA7 = 0x40
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};
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bool _interrupt_line;
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// expected to be overridden
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uint8_t get_port_input(int port) { return 0xff; }
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@ -181,10 +192,10 @@ template <class T> class MOS6532 {
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inline void evaluate_interrupts()
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{
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set_irq_line(
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_interrupt_line =
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((_interrupt_status&InterruptFlag::Timer) && _timer.interrupt_enabled) ||
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((_interrupt_status&InterruptFlag::PA7) && _a7_interrupt.enabled)
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);
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((_interrupt_status&InterruptFlag::PA7) && _a7_interrupt.enabled);
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set_irq_line(_interrupt_line);
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}
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};
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@ -20,7 +20,7 @@ class MOS6532Tests: XCTestCase {
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func testOneTickTimer() {
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with6532 {
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// set a count of 128 at single-clock intervals
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$0.setValue(128, forRegister:4)
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$0.setValue(128, forRegister:0x14)
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// run for one clock and the count should now be 127
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$0.runForCycles(1)
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@ -32,11 +32,11 @@ class MOS6532Tests: XCTestCase {
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}
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}
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// TODO: the test below makes the assumption that divider phase is flexible; verify
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// TODO: the tests below makes the assumption that divider phase is flexible; verify
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func testEightTickTimer() {
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with6532 {
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// set a count of 28 at eight-clock intervals
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$0.setValue(28, forRegister:5)
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$0.setValue(28, forRegister:0x15)
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// run for seven clock and the count should still be 28
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$0.runForCycles(7)
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@ -59,4 +59,96 @@ class MOS6532Tests: XCTestCase {
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XCTAssert($0.valueForRegister(4) == 0xfa, "Timer should decrement after eighth cycle")
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}
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}
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func testTimerInterrupt() {
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with6532 {
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// set a count of 1 at single-clock intervals
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$0.setValue(1, forRegister:0x1c)
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// run for one clock and the count should now be zero
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$0.runForCycles(1)
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// interrupt shouldn't be signalled yet, bit should not be set
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XCTAssert(!$0.irqLine, "IRQ line should not be set")
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XCTAssert($0.valueForRegister(5) == 0x00, "Counter interrupt should not be set")
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// run for one more clock
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$0.runForCycles(1)
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// the interrupt line and bit should now be set
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XCTAssert($0.irqLine, "IRQ line should be set")
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XCTAssert($0.valueForRegister(5) == 0x80, "Counter interrupt should be set")
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// writing again to the timer should clear both
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$0.setValue(1, forRegister:0x1c)
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XCTAssert(!$0.irqLine, "IRQ line should be clear")
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XCTAssert($0.valueForRegister(5) == 0x00, "Counter interrupt should not be set")
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}
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}
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// MARK: PA7 interrupt tests
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func testPA7InterruptDisabled() {
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with6532 {
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// disable edge detection
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$0.setValue(0, forRegister:4)
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// set output mode for port a
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$0.setValue(0xff, forRegister:1)
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// toggle bit 7 of port a in both directions
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$0.setValue(0x80, forRegister:0)
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$0.setValue(0x00, forRegister:0)
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$0.setValue(0x80, forRegister:0)
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// confirm that the interrupt flag is set but the line is not
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XCTAssert(!$0.irqLine, "IRQ line should not be set")
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XCTAssert($0.valueForRegister(5) == 0x40, "Timer interrupt bit should be set")
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// reading the status register should have reset the interrupt flag
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XCTAssert($0.valueForRegister(5) == 0x00, "Timer interrupt bit should be reset")
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}
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}
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func testPA7LeadingEdge() {
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with6532 {
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// seed port a is high; ensure interrupt bit is clear
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$0.setValue(0x00, forRegister:0)
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$0.valueForRegister(5)
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// enable leading edge detection
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$0.setValue(0, forRegister:7)
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// set output mode for port a
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$0.setValue(0xff, forRegister:1)
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// toggle bit 7 of port a in a leading direction
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$0.setValue(0x80, forRegister:0)
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// confirm that both the interrupt flag are the line are set
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XCTAssert($0.irqLine, "IRQ line should be set")
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XCTAssert($0.valueForRegister(5) == 0x40, "Timer interrupt bit should be set")
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}
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}
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func testPA7TrailingEdge() {
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with6532 {
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// seed port a is high; ensure interrupt bit is clear
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$0.setValue(0x80, forRegister:0)
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$0.valueForRegister(5)
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// enable trailing edge detection
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$0.setValue(0, forRegister:6)
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// set output mode for port a
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$0.setValue(0xff, forRegister:1)
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// toggle bit 7 of port a in a rising direction
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$0.setValue(0x00, forRegister:0)
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// confirm that both the interrupt flag are the line are set
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XCTAssert($0.irqLine, "IRQ line should be set")
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XCTAssert($0.valueForRegister(5) == 0x40, "Timer interrupt bit should be set")
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}
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}
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}
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@ -32,4 +32,9 @@ class VanillaRIOT: public MOS::MOS6532<VanillaRIOT> {
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_riot.run_for_cycles((int)numberOfCycles);
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}
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- (BOOL)irqLine
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{
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return _riot.get_inerrupt_line();
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}
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@end
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