6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-06-29 00:29:34 +00:00
Code Issues Projects Releases Wiki Activity

Merge branch 'master' into InAmiga

Browse Source
This commit is contained in:
Thomas Harte 2022-06-15 21:23:30 -04:00
commit fe748507f0
3 changed files with 15 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
Processors/68000Mk2/68000Mk2.hpp
View File

@ -175,17 +175,17 @@ struct Microcycle {
}
/*!
@returns non-zero if this is a byte read and 68000 LDS is asserted.
@returns non-zero if the 68000 LDS is asserted; zero otherwise.
*/
forceinline int lower_data_select() const {
return (operation & SelectByte) & ((*address & 1) << 3);
return ((operation & SelectByte) & (*address & 1)) | (operation & SelectWord);
}
/*!
@returns non-zero if this is a byte read and 68000 UDS is asserted.
@returns non-zero if the 68000 UDS is asserted; zero otherwise.
*/
forceinline int upper_data_select() const {
return (operation & SelectByte) & ~((*address & 1) << 3);
return ((operation & SelectByte) & ~(*address & 1)) | (operation & SelectWord);
}
/*!
@ -229,21 +229,18 @@ struct Microcycle {
}
/*!
@returns the value currently on the high 8 lines of the data bus if any;
@c 0xff otherwise. Assumes this is a write cycle.
@returns the value currently on the high 8 lines of the data bus.
*/
forceinline uint8_t value8_high() const {
const uint8_t values[] = { uint8_t(value->w), value->b};
const uint8_t values[] = { uint8_t(value->w >> 8), value->b};
return values[operation & SelectByte];
}
/*!
@returns the value currently on the low 8 lines of the data bus if any;
@c 0xff otherwise. Assumes this is a write cycle.
@returns the value currently on the low 8 lines of the data bus.
*/
forceinline uint8_t value8_low() const {
const uint8_t values[] = { uint8_t(value->w), value->b};
return values[operation & SelectByte];
return value->b;
}
/*!
@ -394,6 +391,8 @@ template <class BusHandler, bool dtack_is_implicit = true, bool permit_overrun =
class Processor: private ProcessorBase {
public:
Processor(BusHandler &bus_handler) : ProcessorBase(), bus_handler_(bus_handler) {}
Processor(const Processor& rhs) = delete;
Processor& operator=(const Processor& rhs) = delete;
void run_for(HalfCycles duration);

4
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
View File

@ -1091,6 +1091,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// (i) this operand isn't used; or
// (ii) its address calculation will end up conflated with performance,
// so there's no generic bus-accurate approach.
assert(next_operand_ >= 0 && next_operand_ < 2);
if(!(operand_flags_ & (1 << next_operand_))) {
MoveToStateDynamic(perform_state_);
}
@ -1099,6 +1100,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// As above, but for .l.
BeginState(FetchOperand_l):
assert(next_operand_ >= 0 && next_operand_ < 2);
if(!(operand_flags_ & (1 << next_operand_))) {
MoveToStateDynamic(perform_state_);
}
@ -1183,7 +1185,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].high); // nW
effective_address_[1].l += 2;
Access(operand_[next_operand_].low); // nW
Access(operand_[next_operand_].low); // nw
Prefetch(); // np
MoveToStateSpecific(Decode);

2
Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
View File

@ -22,6 +22,8 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
ProcessorBase() {
read_program_announce.address = read_program.address = &program_counter_.l;
}
ProcessorBase(const ProcessorBase& rhs) = delete;
ProcessorBase& operator=(const ProcessorBase& rhs) = delete;
int state_ = std::numeric_limits<int>::min();