119 Commits

Author	SHA1	Message	Date
Thomas Harte	b00be303aa	Remove dead state.	2025-11-07 13:08:12 -05:00
Thomas Harte	7658edca62	Remove unused enum.	2025-11-07 10:49:26 -05:00
Thomas Harte	056028e07b	Put bit restriction on register pointer.	2025-11-07 10:43:14 -05:00
Thomas Harte	45d0f101a7	Switch the BBC Micro to 6502Mk2.	2025-10-26 21:04:59 -04:00
Thomas Harte	2eb94f1b66	Return 0 for write-only and nonexistent registers.	2025-10-20 13:26:22 -04:00
Thomas Harte	02a10ef651	Fall in line with nonsense.	2025-10-02 15:11:01 -04:00
Thomas Harte	a9abc0dd5f	Document a little further.	2025-10-02 09:30:33 -04:00
Thomas Harte	4377c79068	Switch blink rates.	2025-10-02 09:10:12 -04:00
Thomas Harte	514993bc2e	Pull out cursor mask as a separate concern.	2025-10-02 07:56:07 -04:00
Thomas Harte	f279bebc1a	Reduce redundant masking.	2025-10-01 21:59:40 -04:00
Thomas Harte	01d355a247	Rename SizedCounter.	2025-10-01 20:58:34 -04:00
Thomas Harte	7316fe00ee	Support native blink speeds.	2025-09-29 16:13:39 -04:00
Thomas Harte	068726e0ab	Add TODO.	2025-09-24 21:26:04 -04:00
Thomas Harte	89e86ad9bd	Delay publication of the refresh address.	2025-09-24 21:20:20 -04:00
Thomas Harte	174c8dafbf	Resolve potential out-of-phase line counter.	2025-09-24 17:26:40 -04:00
Thomas Harte	90a96293de	Implement interlace-dependent row addressing.	2025-09-24 17:20:04 -04:00
Thomas Harte	84877c4fec	Reenable the cursor; good enough for now.	2025-09-24 14:37:52 -04:00
Thomas Harte	a7cceb5fa9	Avoid circular state dependency.	2025-09-24 14:30:37 -04:00
Thomas Harte	ca6359a597	Reintroduce pixels, proving myself to be off-by-one.	2025-09-24 14:29:25 -04:00
Thomas Harte	b7c3667be1	Work out inadvertent discrepancies.	2025-09-24 14:11:06 -04:00
Thomas Harte	b6dea59db3	This tests lines, not rows.	2025-09-24 13:56:16 -04:00
Thomas Harte	aa51f13743	Reorder to avoid dependencies upon values that mutate.	2025-09-24 13:54:09 -04:00
Thomas Harte	f34ec03ff0	Attempt to fix off-by-one; adopt fixed pixel pattern.	2025-09-24 13:42:17 -04:00
Thomas Harte	1363be59b7	Formalise field size.	2025-09-24 11:17:47 -04:00
Thomas Harte	622c24ef24	This indicates a line, not a row.	2025-09-23 22:36:56 -04:00
Thomas Harte	539b0e49d4	Start in mode 7, reallow interlaced modes.	2025-09-23 14:45:32 -04:00
Thomas Harte	0c42976312	Add notes to self.	2025-09-23 14:42:16 -04:00
Thomas Harte	67e1773495	This flag covers rows, not lines.	2025-09-23 14:29:00 -04:00
Thomas Harte	a199b64aa0	Clarify naming, attempt better to conform to FPGA precedent.	2025-09-23 14:27:21 -04:00
Thomas Harte	0349931953	Shuffle declare order.	2025-09-22 13:21:48 -04:00
Thomas Harte	d612a385d2	Dig in further on types.	2025-09-22 13:20:10 -04:00
Thomas Harte	ed4f299d55	Start formalising types.	2025-09-22 13:09:30 -04:00
Thomas Harte	66bfb86d42	Introduce SizedCounter as start of CRTC reworking.	2025-09-22 12:46:39 -04:00
Thomas Harte	eef0ee8180	Support cursor to end of row.	2025-09-20 08:27:58 -04:00
Thomas Harte	12f063c178	Hack in a stable sync.	2025-09-17 21:35:41 -04:00
Thomas Harte	ff69709926	Disable interlace support.	2025-09-15 23:53:36 -04:00
Thomas Harte	691292501a	Promote constexprs to static.	2025-09-10 21:46:44 -04:00
Thomas Harte	d177549dd6	Reduce more indentation.	2025-08-29 23:56:35 -04:00
Thomas Harte	2c2216afae	Further eliminate file-relative includes.	2025-02-28 13:18:48 -05:00
Thomas Harte	3a0f4a0bfc	Improve constness, formatting.	2024-12-01 18:09:19 -05:00
Thomas Harte	088bc14b11	Begin a reformatting of components.	2024-11-29 22:43:54 -05:00
Thomas Harte	9acc80260f	Eliminate phases due to lack of evidence.	2024-10-09 11:59:27 -04:00
Thomas Harte	7759fb7e68	Add TODO.	2024-10-09 11:48:08 -04:00
Thomas Harte	0d71724598	Eliminate extra-scanline flag.	2024-10-09 11:45:32 -04:00
Thomas Harte	ae436f7a51	Fix conflicting usages of EOF.	2024-10-09 11:16:12 -04:00
Thomas Harte	43ac20cbd2	Fix non-interlaced frame length.	2024-10-07 21:50:56 -04:00
Thomas Harte	2d90868f5c	Reinstitute cursor.	2024-10-07 21:13:44 -04:00
Thomas Harte	60987ae4a7	Round out interlaced output.	2024-10-07 20:53:41 -04:00
Thomas Harte	65c1d99120	Add, disable some logging.	2024-10-05 22:30:53 -04:00
Thomas Harte	35acf88847	Take a swing at adding an adjustment period.	2024-10-03 22:07:46 -04:00