45 Commits

Author	SHA1	Message	Date
Thomas Harte	d3ed485e7a	Take another big swing at indentation, some consts.	2024-12-01 21:44:14 -05:00
Thomas Harte	8b88d1294d	Remove errant spaces.	2024-12-01 09:04:32 -05:00
Thomas Harte	394fe0f1f1	Improve formatting, constness in 68k and ARM instruction set implementations.	2024-12-01 08:20:24 -05:00
Thomas Harte	5a84e98256	Fix trans for instruction fetches.	2024-04-29 21:54:59 -04:00
Thomas Harte	8e64a854fc	Ensure all routes return; mildly decrease conditionals.	2024-04-22 21:56:53 -04:00
Thomas Harte	ea3eef3817	Put interrupts into pipeline, without delay.	2024-04-19 22:21:23 -04:00
Thomas Harte	83eac172c9	Revoke in-pipeline interrupts. ... I'm unclear on what timing should apply here really.	2024-04-19 21:46:09 -04:00
Thomas Harte	5b13d3e893	Attempt the prefetch portion of a pipeline.	2024-04-19 21:30:15 -04:00
Thomas Harte	da520de9ef	Further appease GCC.	2024-04-17 22:38:32 -04:00
Thomas Harte	e680a973b0	Appease GCC with a 'default'.	2024-04-17 22:17:24 -04:00
Thomas Harte	7d8a364658	Reimplement LDM and STM.	2024-04-04 21:59:18 -04:00
Thomas Harte	41c471ca52	Add a force-user-aware accessor.	2024-04-04 20:17:44 -04:00
Thomas Harte	55f92e2411	Adjust data abort address.	2024-03-23 20:31:47 -04:00
Thomas Harte	9ea3e547ee	Fix IRQ/FIQ return addresses.	2024-03-22 21:42:34 -04:00
Thomas Harte	85a738acff	Get rigorous on exception addresses.	2024-03-19 15:03:31 -04:00
Thomas Harte	9d858bc61b	IRQ and FIQ should also store PC+4.	2024-03-18 14:08:08 -04:00
Thomas Harte	1c1d2891c7	Adjust IRQ/FIQ return addresses.	2024-03-15 21:59:38 -04:00
Thomas Harte	1979d2e5ba	Don't set interrupt flags before capture.	2024-03-15 21:34:39 -04:00
Thomas Harte	c25d0e8843	Correctly capture mode upon exception.	2024-03-15 18:39:56 -04:00
Thomas Harte	5d6bb11eb7	Add return.	2024-03-12 11:37:15 -04:00
Thomas Harte	c6b91559e1	Attempt to wire up timer interrupts.	2024-03-12 11:34:31 -04:00
Thomas Harte	6efc41ded7	Come to conclusion on R15; fix link values.	2024-03-12 10:42:09 -04:00
Thomas Harte	d059e7c5d8	Disallow copying.	2024-03-09 15:10:55 -05:00
Thomas Harte	fdef8901ab	Double down on uint32_t.	2024-03-08 14:13:34 -05:00
Thomas Harte	ca1c3dc005	Add extra comments. ... To persuade myself in the future.	2024-03-08 11:36:17 -05:00
Thomas Harte	1b7c3644f4	Eliinate meaningless 'const'.	2024-03-04 14:09:27 -05:00
Thomas Harte	0cdca12e06	Resolve type mismatches.	2024-03-04 13:53:46 -05:00
Thomas Harte	61d4c69e45	Fix template parameter reference.	2024-03-04 13:25:40 -05:00
Thomas Harte	79865e295b	Avoid ambiguous template parameter; use standard type.	2024-03-04 12:20:40 -05:00
Thomas Harte	230e9c6327	Obscure active.	2024-03-03 21:43:30 -05:00
Thomas Harte	11c4d2f09e	Add further exposition.	2024-03-03 21:38:27 -05:00
Thomas Harte	b42a6e447d	Tie down more corners.	2024-03-03 21:29:53 -05:00
Thomas Harte	62da0dee7f	Unify reads.	2024-03-02 23:15:17 -05:00
Thomas Harte	1663d3d9d1	Introduce disaster of an attempted test run.	2024-03-02 22:40:12 -05:00
Thomas Harte	42ba6d1281	Relocate execution code appropriately.	2024-03-01 15:02:47 -05:00
Thomas Harte	5759798ad7	Deal with downward write order.	2024-02-29 14:34:20 -05:00
Thomas Harte	fd2c5b6679	Make a quick first attempt at memory accesses.	2024-02-29 10:18:09 -05:00
Thomas Harte	3b320bcdef	Update coprocessor interface.	2024-02-28 14:43:31 -05:00
Thomas Harte	3368bdb99f	Document exceptions, partly for my future self.	2024-02-28 14:34:31 -05:00
Thomas Harte	4d400c3cb7	Add easy exceptions.	2024-02-28 14:25:12 -05:00
Thomas Harte	474f9da3c2	Add banked registers.	2024-02-28 14:09:05 -05:00
Thomas Harte	60d1b36e9a	Implement registers side.	2024-02-28 10:25:14 -05:00
Thomas Harte	5a48c15e46	Add scheduler side of PC writeback.	2024-02-28 10:15:23 -05:00
Thomas Harte	d6bf1808f9	Take a swing at PC-as-input.	2024-02-28 09:33:05 -05:00
Thomas Harte	b676153d21	State intention to merge status with other registers.	2024-02-27 15:36:34 -05:00