Thomas Harte
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7af3de010e
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Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
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2017-08-23 22:25:31 -04:00 |
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Thomas Harte
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95a6b0f85c
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Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
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2017-06-22 21:09:26 -04:00 |
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Thomas Harte
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50be3a24fe
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Sought to ensure that Mode 1 interrupts aren't happening early. Which they seem not to be.
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2017-06-11 13:30:08 -04:00 |
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Thomas Harte
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b3da16911f
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Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.
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2017-06-03 18:42:54 -04:00 |
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Thomas Harte
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e52892f75b
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Added a test of interrupt mode 1.
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2017-06-03 18:16:13 -04:00 |
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Thomas Harte
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8c41a0f0ed
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Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.
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2017-06-03 17:53:44 -04:00 |
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Thomas Harte
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3e9212aaff
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Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
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2017-06-03 17:41:45 -04:00 |
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