Thomas Harte
eff9a09b9f
Collapse MOVE and NEG[X] similarities.
2022-10-11 21:27:18 -04:00
Thomas Harte
1f19141746
Eliminate BiggerInt
.
2022-10-11 16:19:47 -04:00
Thomas Harte
28093196b9
Convert DIVU/DIVS logic to a template.
2022-10-11 16:16:53 -04:00
Thomas Harte
eb206a08d9
Templatise MULU/MULS.
2022-10-11 16:02:20 -04:00
Thomas Harte
b2f005da1b
Collapse SR/CCR bitwise operations into a template.
2022-10-11 15:53:11 -04:00
Thomas Harte
8305a3b46a
Consolidate compare logic.
2022-10-11 12:57:02 -04:00
Thomas Harte
f3f23f90a3
Consolidate repetition in CLR.
2022-10-11 11:22:34 -04:00
Thomas Harte
77bc60bf86
Consolidate BCLR, BCHG and BSET into a macro.
2022-10-11 10:47:55 -04:00
Thomas Harte
ec5d57fefe
Eliminate 64-bit work.
2022-10-11 10:33:28 -04:00
Thomas Harte
58396f0c52
Perform a prima facie conversion of ADD/SUB[/X] from macros to templates.
2022-10-10 22:21:13 -04:00
Thomas Harte
451b730c8e
Avoid returning without value in release builds.
2022-09-09 16:48:12 -04:00
Thomas Harte
72b6ab4389
Provide a route to operation that factors in addressing mode.
2022-09-06 11:26:16 -04:00
Thomas Harte
effe8c102d
Provide a direct to_string
on Operation
.
2022-09-05 21:52:20 -04:00
Thomas Harte
b6f45d9a90
Fix struct/class confusion.
2022-08-10 15:40:46 -04:00
Thomas Harte
8ada73b283
Use the outer switch for addressing mode dispatch, saving a lot of syntax.
2022-06-13 08:57:49 -04:00
Thomas Harte
71e38a6781
Fix decoding of RESET.
2022-06-03 11:15:50 -04:00
Thomas Harte
02b6ea6c46
Factor out would-accept-interrupt test, per uncertainty re: level 7.
2022-06-03 08:31:56 -04:00
Thomas Harte
c3b436fe96
Use int64_t
as an intermediary to avoid x86 exception on INT_MIN/-1.
2022-06-02 21:39:52 -04:00
Thomas Harte
659e4f6987
Include fixed cost of rolls. Which includes providing slightly more information to did_shift
.
2022-06-01 20:30:51 -04:00
Thomas Harte
75e85b80aa
Factor out the common stuff of exception state.
2022-06-01 08:20:33 -04:00
Thomas Harte
73815ba1dd
No need for this hoop jumping here.
2022-06-01 08:20:06 -04:00
Thomas Harte
8ffaf1a8e4
Ensure did_divu/s are performed even upon divide by zero.
2022-05-29 21:18:19 -04:00
Thomas Harte
7788a109b0
Tweak more overtly to avoid divide by zero.
2022-05-29 20:51:50 -04:00
Thomas Harte
3ef53315a2
Don't try to append operands to 'None'.
2022-05-29 15:28:16 -04:00
Thomas Harte
3da720c789
Make requires_supervisor
explicitly compile-time usable.
2022-05-29 14:55:24 -04:00
Thomas Harte
c97245e626
Fix CalcEA timing; make MOVEfromSR a read-modify-write.
2022-05-27 10:32:28 -04:00
Thomas Harte
463fbb07f9
Adapt remaining 68000 tests to use Mk2.
2022-05-25 10:55:17 -04:00
Thomas Harte
9e3c2b68d7
Eliminate potential future implicit conversion warnings.
2022-05-24 11:05:24 -04:00
Thomas Harte
3349bcaaed
Attempt interrupt support.
2022-05-24 10:53:59 -04:00
Thomas Harte
6a442e0136
MOVEM has an immediate first operand.
2022-05-20 20:34:51 -04:00
Thomas Harte
cb77519af8
Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode.
2022-05-20 12:40:09 -04:00
Thomas Harte
ba8592ceae
At least on the 68000, Scc is read-modify-write.
2022-05-20 11:43:26 -04:00
Thomas Harte
452dd3ccfd
Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.
2022-05-20 11:20:23 -04:00
Thomas Harte
eeb6a088b8
Add a tag to avoid duplication.
2022-05-19 15:49:42 -04:00
Thomas Harte
e4c0a89889
Just use the four-bit register number directly.
2022-05-19 15:01:09 -04:00
Thomas Harte
c6c6213460
Bifurcate the fetch-operand flow.
...
Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.
2022-05-19 10:27:51 -04:00
Thomas Harte
3db2de7478
Works 68000 mk2 into the comparative tests.
...
... revealing that I've leant a little too hard on __LINE__.
2022-05-16 20:04:13 -04:00
Thomas Harte
acb63a1307
Pull generalised DIVU/DIVS into a macro.
2022-05-15 20:01:51 -04:00
Thomas Harte
341bf2e480
Repattern DIVS after DIVU.
2022-05-15 16:54:58 -04:00
Thomas Harte
ff8e4754d7
Ensure STOP exits the run loop.
2022-05-14 19:17:32 -04:00
Thomas Harte
27c4d19455
Support STOP.
2022-05-14 11:35:35 -04:00
Thomas Harte
f83954f5b7
Switch to common bit-selection logic.
2022-05-13 15:08:15 -04:00
Thomas Harte
77b56c50e6
Ensure you can't trace into divide-by-zero, etc.
2022-05-13 14:02:56 -04:00
Thomas Harte
002a8c061f
Trim the public interface of Executor
.
2022-05-13 13:55:37 -04:00
Thomas Harte
4299334e24
Clean up some TODOs, eliminate one further conditional.
2022-05-13 11:17:57 -04:00
Thomas Harte
4d03c73222
Ensure that the first instruction of privilege/line1010/etc exceptions isn't traced.
2022-05-13 11:08:22 -04:00
Thomas Harte
7a2fd93d08
Document BusHandler interface.
2022-05-13 10:59:36 -04:00
Thomas Harte
5b67c9bf4a
MOVE to SR requires supervisor privileges.
2022-05-13 09:01:03 -04:00
Thomas Harte
6c854e8ecc
Simplify is_supervisor
semantics.
2022-05-13 07:53:40 -04:00
Thomas Harte
2e796f31d4
Support interrupts; documentation to come.
2022-05-12 20:52:24 -04:00
Thomas Harte
2fa6b2301b
Move string logic into Preinstruction
.
2022-05-12 19:46:08 -04:00
Thomas Harte
a6e4d23c29
Tidy up primarily as per PatickvL's comments.
...
... though pulling the flag values out of an enum and into a namespace is entirely my own contribution, to keep them in their own namespace but having them overtly be ints.
2022-05-12 16:23:07 -04:00
Thomas Harte
6d43576db7
Remove errant semicolon.
2022-05-12 16:21:36 -04:00
Thomas Harte
b7d1bff0c7
Eliminate branches from ABCD.
2022-05-12 15:25:01 -04:00
Thomas Harte
79c5af755f
Eliminate branches from SBCD.
2022-05-12 15:18:03 -04:00
Thomas Harte
c6d84e7e60
Use Status::FlagT
pervasively.
2022-05-12 11:42:33 -04:00
Thomas Harte
192513656a
After much guesswork, fix SBCD and thereby pass flamewing tests.
2022-05-12 11:39:01 -04:00
Thomas Harte
f3c1b1f052
Name flags, remove closing underscores on exposed data fields.
2022-05-12 08:19:41 -04:00
Thomas Harte
bd61c72007
Mutate SBCD to correct values, though not yet statuses.
2022-05-12 07:22:26 -04:00
Thomas Harte
0efeea1294
Slightly improve SBCD. Not there yet though.
2022-05-12 07:07:21 -04:00
Thomas Harte
a9902fc817
Fix ABCD when the result has an invalid lower digit.
2022-05-11 16:31:27 -04:00
Thomas Harte
d492156453
Add noreturn
attribute as a warning.
2022-05-11 10:51:48 -04:00
Thomas Harte
96af3d5ec5
Fix infinite inner/outer loop.
2022-05-11 10:26:12 -04:00
Thomas Harte
69ba14e34e
Support the trace flag.
2022-05-11 09:39:15 -04:00
Thomas Harte
943c924382
Add missing: MOVE to/from USP, RESET.
2022-05-11 07:52:23 -04:00
Thomas Harte
4b97427937
Remove further magic constants.
2022-05-11 07:00:35 -04:00
Thomas Harte
ab8e1fdcbf
Take a swing at access faults and address errors.
2022-05-10 16:20:30 -04:00
Thomas Harte
477979c275
Fully formulate and document the flow controller.
2022-05-10 10:34:07 -04:00
Thomas Harte
c635720a09
Tidy up; provide a notification for bit-change operations.
2022-05-10 08:23:25 -04:00
Thomas Harte
f2a6a12f79
Remove further vestiges of timing.
2022-05-09 20:58:51 -04:00
Thomas Harte
7445c617bc
Start removing 68000-specific timing calculations.
2022-05-09 20:32:02 -04:00
Thomas Harte
8e7340860e
Minor thematic rearrangement.
2022-05-09 16:35:17 -04:00
Thomas Harte
2ca1eb4cf8
Move set_pc
into the operation-specific group.
2022-05-09 16:20:15 -04:00
Thomas Harte
0af8660181
Remove add_pc
and decline_branch
in favour of operation-specific signals.
2022-05-09 16:19:25 -04:00
Thomas Harte
2f7cff84d9
Enable missing rotates and shifts.
2022-05-09 11:26:01 -04:00
Thomas Harte
8e5650fde9
Clean up Instruction.hpp.
2022-05-09 10:13:42 -04:00
Thomas Harte
539932dc56
Provide function codes. TODO: optionally.
2022-05-09 09:18:02 -04:00
Thomas Harte
e35de357fa
Route reads and writes through a common path.
2022-05-08 17:17:46 -04:00
Thomas Harte
0818fd7828
Ensure no status updates fall through the cracks.
2022-05-07 21:29:12 -04:00
Thomas Harte
98cb9cc1eb
Fix CHK operand size.
2022-05-07 21:16:44 -04:00
Thomas Harte
bf8c97abbb
Permit TRAP, TRAPV and CHK to push the next PC rather than the current.
2022-05-07 20:32:39 -04:00
Thomas Harte
ad6cf5e401
Pull out magic constant, simplify sp
and TAS
.
2022-05-07 20:20:24 -04:00
Thomas Harte
2b3900fd14
Fix LINK A7.
2022-05-07 08:15:26 -04:00
Thomas Harte
1defeca1ad
Implement RTS, RTR, RTE.
2022-05-06 12:30:49 -04:00
Thomas Harte
ac6a9ab631
Fix TAS Dn.
2022-05-06 12:23:04 -04:00
Thomas Harte
8176bb6f79
Expose issues with TST and TAS.
2022-05-06 12:18:56 -04:00
Thomas Harte
9c266d4316
Proceed to unimplemented TST.
2022-05-06 11:33:57 -04:00
Thomas Harte
190a351a29
Fix address writeback.
2022-05-06 09:56:01 -04:00
Thomas Harte
607ddd2f78
Preserve MOVEM order in Operation
.
2022-05-06 09:45:06 -04:00
Thomas Harte
fed79a116f
Be overt about the size being described here.
2022-05-06 09:22:38 -04:00
Thomas Harte
5db0ea0236
Add note for my tomorrow self.
2022-05-05 21:11:02 -04:00
Thomas Harte
06fe320cc0
Correct source counting, but this leaves the operands still being the wrong way around.
2022-05-05 21:06:53 -04:00
Thomas Harte
f7991e18de
Makes a failed attempt to implement MOVEM to registers.
2022-05-05 20:32:21 -04:00
Thomas Harte
d7d0a5c15e
Implement MOVEM to memory.
2022-05-05 18:51:29 -04:00
Thomas Harte
47f4bbeec6
Switch to a contiguous block of 16 registers.
2022-05-05 15:31:59 -04:00
Thomas Harte
9ab70b340c
Route MOVEM appropriately.
2022-05-05 12:42:57 -04:00
Thomas Harte
70cdc2ca9f
Fix MOVEP to register.
...
Advance to lack of MOVEM.
2022-05-05 12:37:47 -04:00
Thomas Harte
f63a872387
BTST does not write back.
2022-05-05 12:32:15 -04:00
Thomas Harte
67462c2f92
Rewire MOVEP.
2022-05-05 12:27:36 -04:00
Thomas Harte
4a4e786060
Hit a realisation: write-back isn't going to work with MOVEP as formulated.
2022-05-05 09:26:26 -04:00
Thomas Harte
665f2d4c00
Attempts MOVEP.
2022-05-05 09:00:33 -04:00
Thomas Harte
64586ca7ba
Implement BTST/etc.
2022-05-04 20:57:22 -04:00
Thomas Harte
15c90e546f
Fix rotates and shifts to memory.
2022-05-04 19:44:59 -04:00
Thomas Harte
5aabe01b6d
Mostly fix LINK and UNLK.
2022-05-04 08:41:55 -04:00
Thomas Harte
5d1d94848c
Take a bash at LINK and UNLK.
2022-05-04 08:26:11 -04:00
Thomas Harte
7d10976e08
Add LINK and UNLINK to operand_flags
.
2022-05-03 20:51:02 -04:00
Thomas Harte
d3b55a74a5
Fix LEA, proceed to non-functional LINK and UNLK.
2022-05-03 20:45:36 -04:00
Thomas Harte
de58ec71fd
Fix EXT, SWAP.
2022-05-03 20:17:36 -04:00
Thomas Harte
052ba80fd7
Add enough wiring to complete but fail EXT and JMP/JSR.
2022-05-03 15:49:55 -04:00
Thomas Harte
39f0ec7536
Get far enough through CHK to realise that MOVEM probably needs to be divided by direction.
2022-05-03 15:40:04 -04:00
Thomas Harte
af973138df
Correct decoding of Bcc.b, satisfying Bcc and BSR tests.
2022-05-03 15:32:54 -04:00
Thomas Harte
5a87506f3d
Fix Bcc, making decision that add_pc
is relative to start of instruction.
2022-05-03 15:21:42 -04:00
Thomas Harte
90f0005cf2
Proceed to failing Bcc and flagging up my lack of an implementation for BSR.
2022-05-03 14:45:49 -04:00
Thomas Harte
d8b3748d24
Fix Scc size, DBcc behaviour.
2022-05-03 14:40:51 -04:00
Thomas Harte
1b224c961e
Fix Scc, add operand flags for DBcc.
2022-05-03 14:23:57 -04:00
Thomas Harte
b6ffff5bbd
Distinguish [ADD/SUB]QA from [ADD/SUB]Q.
2022-05-03 14:17:26 -04:00
Thomas Harte
b3cf13775b
Consume operand_flags into Instruction.hpp.
2022-05-03 11:09:57 -04:00
Thomas Harte
c61809f0c4
Add CMPAl
.
2022-05-03 09:20:02 -04:00
Thomas Harte
2f2d6bc08b
Correct CMPw.
2022-05-03 09:05:34 -04:00
Thomas Harte
1bb809098c
Switch — messily — to a more compact way of indicating sequence.
2022-05-03 09:04:54 -04:00
Thomas Harte
011506f00d
Add basic exceptions.
2022-05-02 21:27:58 -04:00
Thomas Harte
25ab478461
Fix immediate byte and word fetches.
2022-05-02 20:17:44 -04:00
Thomas Harte
fc9a35dd04
Test add/sub, add an exception for invalid Sequence
s.
2022-05-02 20:09:38 -04:00
Thomas Harte
7efe30f34c
Fix (d8, _, Xn) calculation.
2022-05-02 15:09:59 -04:00
Thomas Harte
3827ecd6d3
Proceed to complete test running.
2022-05-02 12:57:45 -04:00
Thomas Harte
14532867a4
Sneaks towards testing EXT.
2022-05-02 08:00:56 -04:00
Thomas Harte
73f340586d
Proceed to building, but failing tests.
2022-05-02 07:45:07 -04:00
Thomas Harte
56fe00c5fb
Correct errors preparatory to Executor's lack of flow controller actions.
2022-05-01 20:40:57 -04:00
Thomas Harte
3c26177239
Provide both compile- and run-time operation selection options.
2022-05-01 17:39:56 -04:00
Thomas Harte
fe8f0d960d
Equivocate.
...
(Specifically: addresses cannot generally be obtained in advance, as they are often the product of registers, but things like displacements, immediate values and absolute addresses can)
2022-05-01 15:30:03 -04:00
Thomas Harte
c72caef4fd
Correct further size specifiers.
2022-05-01 15:21:58 -04:00
Thomas Harte
0720a391e8
Correct address register mutations.
2022-05-01 15:18:06 -04:00
Thomas Harte
d16ac70a50
Correct include path.
2022-05-01 15:14:12 -04:00
Thomas Harte
fc8e020436
Improve field name.
2022-05-01 15:12:13 -04:00
Thomas Harte
6b073c6067
Attempt to round out addressing modes, shift to a header, as per templating on BusHandler.
2022-05-01 15:10:54 -04:00
Thomas Harte
0b19bbff8d
Marginally refactor, to avoid repetition of read/write branch.
2022-05-01 13:09:28 -04:00
Thomas Harte
42927c1e32
Establish more of the 680x0 executor loop.
2022-05-01 13:00:20 -04:00
Thomas Harte
df999978f1
Figure out what the call to perform
should look like.
...
Albeit that this class doesn't currently offer any of the proper flow control actions.
2022-04-30 20:34:44 -04:00
Thomas Harte
43cd740a7b
Shuffle Step
to give meaning to the LSB.
2022-04-30 20:33:35 -04:00
Thomas Harte
52f355db24
Decision: operation is not a template parameter. Hence can use condition as fully typed.
2022-04-30 14:08:51 -04:00
Thomas Harte
a86c5ccdc9
Merge branch '68000Perform' of github.com:TomHarte/CLK into 68000Perform
2022-04-30 14:02:23 -04:00
Thomas Harte
e532562108
Merge branch 'master' into 68000Perform
2022-04-30 14:02:17 -04:00
Thomas Harte
8d24c00df2
Include decoded condition in Preinstruction.
2022-04-30 09:00:47 -04:00
Thomas Harte
f4074e0bba
Add basic status.
2022-04-30 08:38:28 -04:00
Thomas Harte
e4426dc952
Introduce calculate EA steps.
2022-04-29 20:30:48 -04:00
Thomas Harte
9359f6477b
Start drafting an Executor.
2022-04-29 17:12:06 -04:00
Thomas Harte
a103f30d51
Attempt to game out LEA, PEA. Add various special MOVEs.
2022-04-29 14:43:58 -04:00
Thomas Harte
78b60dbd1a
Evict MOVEM and MOVEP, enable TRAP and TRAPV, complete CHK.
2022-04-29 14:43:30 -04:00
Thomas Harte
cde75a1c00
Make steps more visible.
2022-04-29 11:26:39 -04:00
Thomas Harte
b9d243552c
MOVEs don't read from operand 2.
2022-04-29 11:22:06 -04:00
Thomas Harte
85242ba896
Add to Xcode project, template on Model as per CLR being odd. Fill in some obvious answers.
2022-04-29 11:10:14 -04:00
Thomas Harte
d16dab6f62
Starts introducing a sequencer, to resolve responsibility of perform
.
2022-04-29 10:40:19 -04:00
Thomas Harte
8066b19f93
Correct typos.
2022-04-29 07:57:02 -04:00
Thomas Harte
abd2a831a3
Added a further ambiguity.
2022-04-29 05:08:44 -04:00
Thomas Harte
824d3ae3f7
Conclusion: a union does produce better code.
...
(But needn't be so verbose)
2022-04-29 04:51:02 -04:00
Thomas Harte
727a14c6f9
Add notes for myself on decisions yet to make.
2022-04-29 03:53:17 -04:00
Thomas Harte
13d20137d3
Tackle two lingering references to exception_handler.
2022-04-29 03:38:23 -04:00
Thomas Harte
9680566595
Include in automated build, temporarily.
2022-04-28 20:42:44 -04:00
Thomas Harte
33c9ea2cf7
A flow controller feels more natural than an exception handler.
2022-04-28 20:42:04 -04:00
Thomas Harte
1d8d2b373b
Port all simple instruction bodies.
2022-04-28 16:55:47 -04:00
Thomas Harte
611b472b12
Add evaluate_condition
, to check standard 68000 condition codes.
2022-04-28 16:54:57 -04:00
Thomas Harte
bb73eb0db3
Start working on an isolation of 68000 instruction execution.
2022-04-28 15:35:40 -04:00
Thomas Harte
39261436c8
Remove unused type alias.
2022-04-27 19:53:32 -04:00
Thomas Harte
5e355383df
Correct SIB test.
2022-04-27 19:53:15 -04:00
Thomas Harte
9cbbb6e508
Adjust path to match namespace; add to Qt project.
2022-04-27 08:05:36 -04:00
Thomas Harte
8902bb1af0
Include size and supervisor flag in Preinstruction.
2022-04-26 19:44:02 -04:00
Thomas Harte
baf1bd354d
Avoid packing/unpacking of operands.
2022-04-26 19:37:07 -04:00
Thomas Harte
539c2985aa
Fill in size table, define quick
to return a uint32_t
.
2022-04-26 12:30:14 -04:00
Thomas Harte
5c356e15b5
Completes requires_supervisor
.
2022-04-25 20:05:45 -04:00
Thomas Harte
8ff0b71b29
Subsume MOVEQ into MOVE.l; add missing invalid_operands.
2022-04-25 19:58:19 -04:00
Thomas Harte
8f8f201186
Complete transition to simple AND-based verification.
2022-04-25 16:23:16 -04:00
Thomas Harte
0c688757b0
Adapt the last of the MOVEs, TAS, NOT, SUB and TST.
2022-04-25 16:05:44 -04:00
Thomas Harte
5778e92e70
Adapt MOVE, DIV, MUL, OR.
2022-04-25 15:43:25 -04:00
Thomas Harte
3268ea42ff
Translate SUB, PEA.
2022-04-25 12:41:41 -04:00
Thomas Harte
1538500903
Add enough to make AND masks the default case.
2022-04-25 12:30:44 -04:00
Thomas Harte
6ca30a16ca
Update JMP, JSR.
2022-04-25 12:05:07 -04:00
Thomas Harte
e6dc2e0d31
Add EXG, EXT.
2022-04-25 11:49:14 -04:00
Thomas Harte
9bbd1390c1
Add new-style validation of EORI to CCR, move EXG decoding into page navigation.
2022-04-25 11:43:30 -04:00
Thomas Harte
27f8db6e8b
Update DBcc, DIVU/DIVS, EOR.
2022-04-25 09:49:18 -04:00
Thomas Harte
dda0c0e097
Update CMPM, CMPI.
2022-04-25 09:39:22 -04:00
Thomas Harte
f5ea5c26a3
Translate CHK, CLR, CMP, CMPA.
2022-04-24 21:05:00 -04:00
Thomas Harte
d01fa96177
Port BSR, BTST.
2022-04-24 20:49:41 -04:00
Thomas Harte
03caa53863
Translate BSET.
2022-04-24 19:58:10 -04:00
Thomas Harte
4f4a2e6d92
Translate ASL, ASR, Bcc, BCHG, BCLR.
2022-04-24 19:53:54 -04:00
Thomas Harte
87178ed725
Port AND.
2022-04-24 15:12:18 -04:00
Thomas Harte
94e5436f6e
Attempt a more compact retelling.
2022-04-24 14:47:14 -04:00
Thomas Harte
b965f2053a
Start experimenting with a simple AND for operand validation.
2022-04-24 10:43:06 -04:00
Thomas Harte
edee078f0a
Eliminate last set of failures.
2022-04-22 20:57:45 -04:00
Thomas Harte
d4b766bf3f
Introduce directional ADD/SUB/AND/OR.
...
Just 512 failures to go.
2022-04-22 20:37:09 -04:00
Thomas Harte
72772c9a83
Remove branch from combined_mode
.
...
On x86 it was probably only a conditional move, but this is fine.
2022-04-22 15:11:41 -04:00
Thomas Harte
4c806d7c51
Tidy up slightly, ahead of a final push to getting complete test success.
...
After which I can start undoing style errors.
2022-04-22 14:51:25 -04:00
Thomas Harte
96afcb7a43
Introduce remainder of tests.
2022-04-22 14:33:43 -04:00
Thomas Harte
efeee5160e
Add tests for RTE, RTR, TRAP, TRAPV, CHK.
2022-04-22 10:06:39 -04:00
Thomas Harte
06fb502047
Add MUL/DIV tests and exclusions.
2022-04-22 09:47:16 -04:00
Thomas Harte
977192f480
Resolve D-page decoding errors.
...
In particular: that I'd overlooked CMPM, and was treating NOT as two-operand.
2022-04-22 09:24:16 -04:00
Thomas Harte
cf66d9d38d
Add failing tests for EOR, NOT, OR; disambiguate EOR vs CMP.
2022-04-21 20:36:04 -04:00
Thomas Harte
25eeff8fc5
Correct CMP decoding, correct AND as far as asymmetry of Dn, Dn.
2022-04-21 20:14:52 -04:00
Thomas Harte
bf9fc0ae96
Correct decoding of BSR.
2022-04-21 16:24:34 -04:00
Thomas Harte
a8a1a74b79
Correct BSRb quick value.
2022-04-21 16:13:06 -04:00
Thomas Harte
549e440f7c
Add 'quick' decoding and testing.
2022-04-21 16:05:00 -04:00
Thomas Harte
45c02c31f8
Add MOVEM exclusions.
2022-04-21 15:47:34 -04:00
Thomas Harte
b6b092d124
Add tests, exclusions for rest of shift/roll group.
2022-04-21 11:26:56 -04:00
Thomas Harte
3af93ada6f
Test and correct Bcc, BSR, CLR, NEGX, NEG.
2022-04-20 20:19:56 -04:00
Thomas Harte
dc16928f74
Add appropriate exclusions for JSR, JMP, Scc.
2022-04-20 16:56:26 -04:00
Thomas Harte
80ff146620
Add CMP, CMPA and TST tests and exclusions.
2022-04-20 16:29:45 -04:00
Thomas Harte
d4fe9d8166
Complete BTST/etc exclusions.
2022-04-20 16:16:24 -04:00
Thomas Harte
85a0af03c1
Import more standard JSON; start validating.
2022-04-20 09:17:00 -04:00
Thomas Harte
dc43f5605b
Give MOVEPs precedence.
2022-04-20 08:40:56 -04:00
Thomas Harte
fab064641f
Add Move[to/from][SR/CCR/USP] tests, correct decodings.
2022-04-20 07:59:13 -04:00
Thomas Harte
316e9681cc
Weed out false PEAs.
2022-04-19 20:34:08 -04:00
Thomas Harte
4181313cc6
Correct decoding of SWAP.
2022-04-19 20:28:00 -04:00
Thomas Harte
6aabc5e7b0
Test LEA, PEA, add name for MOVEq.
2022-04-19 19:45:51 -04:00
Thomas Harte
343a8e0192
Resolve wrong-headed mapping of LEA to MOVEAl.
2022-04-19 19:36:21 -04:00
Thomas Harte
ef87d09cfa
Clear up MOVEs, fail on MOVEAs.
2022-04-19 17:13:23 -04:00
Thomas Harte
d21c67f237
Don't permit byte move from address register.
2022-04-19 16:49:26 -04:00
Thomas Harte
de40fed248
Test MOVEs and add operand validation.
2022-04-19 16:31:03 -04:00
Thomas Harte
76d7e0e1f8
Test and correct SUBs.
2022-04-19 16:27:20 -04:00
Thomas Harte
1f585d67b6
ADDA: correct decoding, add validation.
2022-04-19 14:43:01 -04:00
Thomas Harte
5b22e94a4b
Map invalid reg+mode combinations to AddressingMode::None; add validation of ADDs and decoding of ADDX.
2022-04-19 14:36:36 -04:00
Thomas Harte
7749aef6b6
Improve const correctness.
2022-04-19 14:35:40 -04:00
Thomas Harte
5de8fb0d08
Disallow four illegal NBCD addressing modes.
2022-04-19 09:59:02 -04:00
Thomas Harte
19f7335926
Add post validation step.
2022-04-19 09:44:02 -04:00
Thomas Harte
99f4cd867d
Decode the two EXTs.
2022-04-19 08:42:17 -04:00
Thomas Harte
93fe3459fd
The quick value won't always fit in reg; turf the problem elsewhere.
2022-04-19 08:37:35 -04:00
Thomas Harte
1abd3bd7f3
Decode SWAP.
2022-04-19 08:37:13 -04:00
Thomas Harte
fc4fd41be4
Reorder from most specific to least.
2022-04-19 08:00:52 -04:00
Thomas Harte
e4c6251ef5
Express the BSR/Bcc.l test properly.
2022-04-18 14:42:31 -04:00
Thomas Harte
7aa250eaf7
Advances to hitting the same absent/present mapping as the old decoder.
2022-04-18 14:41:26 -04:00
Thomas Harte
ff380b686a
Decode MOVEq.
2022-04-18 09:12:45 -04:00
Thomas Harte
d2452f4b68
Fix SUBQ ExtendedOperation mappings.
2022-04-18 09:08:49 -04:00
Thomas Harte
deb9c32a38
Add missing Sccs.
2022-04-18 09:04:17 -04:00
Thomas Harte
440f45b996
Attempt decoding and disambiguation of Scc, DBcc, Bcc and BSR.
2022-04-18 08:55:46 -04:00
Thomas Harte
7d64c4ec66
Add STOP.
2022-04-18 08:29:10 -04:00
Thomas Harte
7fe0d530c1
Add a decoder for TRAP.
2022-04-18 08:05:33 -04:00
Thomas Harte
c944767554
Better document decoding patterns, add LEA and CHK.
2022-04-18 08:00:43 -04:00
Thomas Harte
fde5a1c507
Ensure ADDI, SUBI, etc, provide an operation.
2022-04-18 07:42:30 -04:00
Thomas Harte
1991ed0804
Introduce failing [partial-]test of new 68000 decoder.
2022-04-18 07:23:25 -04:00
Thomas Harte
4eb752b000
Even out tabs.
2022-04-15 20:41:39 -04:00
Thomas Harte
bfb29a58f3
Take another crack at neatness; make LEA overt.
2022-04-15 20:33:59 -04:00
Thomas Harte
f86e455a87
Advance permissively through the 4xxx page to LEA.
2022-04-15 16:01:33 -04:00
Thomas Harte
faa35fe9fc
Decode MOVE and the fixed 0x4xxx set.
2022-04-15 15:40:31 -04:00
Thomas Harte
89b8b59658
Ostensibly completes the 0 line.
2022-04-15 15:33:54 -04:00
Thomas Harte
de55a1adc4
Require a model for decoding; shift a bunch of immediates into ExtendedOperation.
2022-04-15 09:40:37 -04:00
Thomas Harte
d1613025ee
For now, assume the .q actions can be handled inside Preinstruction.
2022-04-13 09:29:12 -04:00
Thomas Harte
cc4431c409
Expand decode to accept a wider array of operations, and then funnel them down.
2022-04-12 16:17:30 -04:00
Thomas Harte
3d5986c55d
Some minor style changes, plus I think I've talked myself into an expanded Operation-tracking enum. Probably.
2022-04-12 14:54:11 -04:00
Thomas Harte
9aeb6ee532
Formally prepare for one- and two-operand instructions.
2022-04-12 09:14:46 -04:00
Thomas Harte
e7f6cc598d
Make first attempt to complete broad phase of decoding.
2022-04-12 09:08:46 -04:00
Thomas Harte
cd465dd121
Decode page E.
2022-04-12 09:04:40 -04:00
Thomas Harte
174b48a14a
Populate lines 9 and D.
2022-04-12 08:57:40 -04:00
Thomas Harte
bca18e7aba
Fill in line decoders for 5, 6 and 7.
...
This leaves 9, D and E to go.
2022-04-12 08:44:32 -04:00
Thomas Harte
17e761d6c6
Add enough code to pages 0–3 to shift problem to decode().
2022-04-12 08:36:44 -04:00
Thomas Harte
c50556dde4
Create empty line decoders.
2022-04-12 08:16:29 -04:00
Thomas Harte
dd5bdd67d7
Add B page and a large chunk of 4.
2022-04-12 07:49:08 -04:00
Thomas Harte
21ac9363e9
Add page 8.
2022-04-11 16:32:57 -04:00
Thomas Harte
8e3cccf4d6
Begins a formalised 68k decoder.
2022-04-11 15:00:55 -04:00
Thomas Harte
bb5cf570e5
Remove conditional, make generic enough for both 32- and 64-bit operation.
2022-04-10 15:18:23 -04:00
Thomas Harte
7002d6d306
Improve accuracy of comment.
2022-04-10 09:37:18 -04:00
Thomas Harte
1b8d8f3a04
Default to 32-bit versions.
2022-04-10 09:35:58 -04:00
Thomas Harte
284440336d
Correct rotate_mask().
2022-04-10 09:31:39 -04:00
Thomas Harte
140ae7a513
Clarify template parameters.
2022-04-10 08:57:09 -04:00
Thomas Harte
7de50b5e2e
Provide 64-bit me, mb and sh. Add direct getter for rotate masks.
2022-04-09 21:08:01 -04:00
Thomas Harte
4652a84b43
Add exposition.
2022-04-09 19:20:13 -04:00
Thomas Harte
9e0755bc86
Introduce overlooked: ld, ldu, rldclx, rldcrx, rldicx, rldiclx, rldicrx, rldimix.
2022-04-09 18:28:51 -04:00
Thomas Harte
da0f7d7907
Rearrange into alphabetical order.
2022-04-09 10:20:03 -04:00
Thomas Harte
88d72bf31d
Fill in more mnemonics.
2022-04-08 10:01:52 -04:00
Thomas Harte
aac2f7dd73
Add missing validations.
2022-04-08 09:47:04 -04:00
Thomas Harte
1f44ad1723
Completes test cases.
2022-04-06 21:09:58 -04:00
Thomas Harte
4ab1857a11
Complete MPC601 commentary.
2022-04-06 20:53:44 -04:00
Thomas Harte
d23c714ec7
Build in an optional post hoc validation.
...
TODO: validate.
2022-04-05 11:23:54 -04:00
Thomas Harte
59a1fde2a1
Fix is_zero_mask.
2022-04-03 20:37:09 -04:00
Thomas Harte
31276de5c3
Complete 'misc instructions' tests.
2022-04-03 20:33:32 -04:00
Thomas Harte
c581aef11d
Test as far as mffs.
2022-04-03 18:29:40 -04:00
Thomas Harte
7f6a955a71
Complete the cmp set.
2022-04-03 15:50:03 -04:00
Thomas Harte
125d97cc41
Complete floating point tests.
2022-04-03 08:55:28 -04:00
Thomas Harte
de7d9ba471
Add further floating point tests.
2022-04-03 08:06:59 -04:00
Thomas Harte
ad54b44235
Begin documentation and testing of the floating point instructions.
2022-04-02 19:58:21 -04:00
Thomas Harte
42532ec0f5
Test floating point loads and stores.
2022-04-02 15:40:17 -04:00
Thomas Harte
b84fa619da
Test integer loads and stores.
2022-04-02 15:27:12 -04:00
Thomas Harte
8a1409184f
Add decoding of lwa.
2022-04-02 10:31:55 -04:00
Thomas Harte
8a3c16a5bc
Add lwa.
2022-04-02 10:26:47 -04:00
Thomas Harte
6343c65ce2
Document further; mftb is optional.
2022-04-02 10:09:58 -04:00
Thomas Harte
d5967f7834
Correct decoding of stwcx. and stdcx.
2022-04-01 20:37:36 -04:00
Thomas Harte
d5f7650ac1
Test synchronising loads and stores, further expand documentation.
2022-04-01 18:30:48 -04:00
Thomas Harte
8f580c256c
Remove explanations; saying nothing is better than giving incomplete advice.
2022-04-01 17:49:34 -04:00
Thomas Harte
7c8f044380
Complete shift tests.
2022-04-01 17:22:32 -04:00
Thomas Harte
8efd506471
Transcribe up to the end of 'e', use extswx
and remove extsw
.
2022-04-01 17:11:57 -04:00
Thomas Harte
e83267751e
Start shuffling parameters into conventional order; expand on cmp–cmpli, dcbf–dcbz.
2022-03-30 20:36:46 -04:00
Thomas Harte
84f0b0a84c
Test rotates.
2022-03-30 16:43:09 -04:00
Thomas Harte
52e7226655
Merge branch 'PowerPCTests' of github.com:TomHarte/CLK into PowerPCTests
2022-03-29 20:50:40 -04:00
Thomas Harte
b89c8decd4
Test addx–divwx and mtcrf; document fields for crand, etc.
2022-03-29 20:48:43 -04:00
Thomas Harte
d783975597
Start offering a list of relevant fields per Operation.
2022-03-29 19:59:21 -04:00
Thomas Harte
5ec291df5c
Merge branch 'PowerPCTests' of github.com:TomHarte/CLK into PowerPCTests
2022-03-29 14:38:28 -04:00
Thomas Harte
0a45355055
Add a few more field comments.
2022-03-29 14:37:21 -04:00
Thomas Harte
99ad40f3e0
Test subfcx, subfx; correct decoding of oe().
2022-03-28 20:39:52 -04:00
Thomas Harte
b9c8016aca
Merge branch 'PowerPCTests' of github.com:TomHarte/CLK into PowerPCTests
2022-03-28 20:20:59 -04:00
Thomas Harte
8ad1f2d4f5
Add bad attempt to catch subfc.
2022-03-28 20:18:41 -04:00
Thomas Harte
dc30581be0
Fix typo; . -> ,
2022-03-28 16:39:55 -04:00
Thomas Harte
2e56b606fa
Improve file division, document some further operations.
2022-03-27 18:44:56 -04:00
Thomas Harte
d84c72afe5
Test loads and stores, and immediate arithmetic.
2022-03-27 08:47:01 -04:00