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8,962 Commits 8 Branches 121 Tags 496 MiB
0af8660181
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53 Commits

Author SHA1 Message Date
Thomas Harte
0af8660181 Remove add_pc and decline_branch in favour of operation-specific signals. 2022-05-09 16:19:25 -04:00
Thomas Harte
539932dc56 Provide function codes. TODO: optionally. 2022-05-09 09:18:02 -04:00
Thomas Harte
98cb9cc1eb Fix CHK operand size. 2022-05-07 21:16:44 -04:00
Thomas Harte
bf8c97abbb Permit TRAP, TRAPV and CHK to push the next PC rather than the current. 2022-05-07 20:32:39 -04:00
Thomas Harte
2b3900fd14 Fix LINK A7. 2022-05-07 08:15:26 -04:00
Thomas Harte
1defeca1ad Implement RTS, RTR, RTE. 2022-05-06 12:30:49 -04:00
Thomas Harte
ac6a9ab631 Fix TAS Dn. 2022-05-06 12:23:04 -04:00
Thomas Harte
8176bb6f79 Expose issues with TST and TAS. 2022-05-06 12:18:56 -04:00
Thomas Harte
9c266d4316 Proceed to unimplemented TST. 2022-05-06 11:33:57 -04:00
Thomas Harte
d478a1b448 Proceed to next failure: PEA. 2022-05-06 10:04:20 -04:00
Thomas Harte
607ddd2f78 Preserve MOVEM order in Operation. 2022-05-06 09:45:06 -04:00
Thomas Harte
06fe320cc0 Correct source counting, but this leaves the operands still being the wrong way around. 2022-05-05 21:06:53 -04:00
Thomas Harte
d7d0a5c15e Implement MOVEM to memory. 2022-05-05 18:51:29 -04:00
Thomas Harte
47f4bbeec6 Switch to a contiguous block of 16 registers. 2022-05-05 15:31:59 -04:00
Thomas Harte
70cdc2ca9f Fix MOVEP to register. 
Advance to lack of MOVEM.
 2022-05-05 12:37:47 -04:00
Thomas Harte
f63a872387 BTST does not write back. 2022-05-05 12:32:15 -04:00
Thomas Harte
46686b4b9c Start testing move. 2022-05-04 20:38:56 -04:00
Thomas Harte
15c90e546f Fix rotates and shifts to memory. 2022-05-04 19:44:59 -04:00
Thomas Harte
5aabe01b6d Mostly fix LINK and UNLK. 2022-05-04 08:41:55 -04:00
Thomas Harte
d3b55a74a5 Fix LEA, proceed to non-functional LINK and UNLK. 2022-05-03 20:45:36 -04:00
Thomas Harte
de58ec71fd Fix EXT, SWAP. 2022-05-03 20:17:36 -04:00
Thomas Harte
052ba80fd7 Add enough wiring to complete but fail EXT and JMP/JSR. 2022-05-03 15:49:55 -04:00
Thomas Harte
39f0ec7536 Get far enough through CHK to realise that MOVEM probably needs to be divided by direction. 2022-05-03 15:40:04 -04:00
Thomas Harte
af973138df Correct decoding of Bcc.b, satisfying Bcc and BSR tests. 2022-05-03 15:32:54 -04:00
Thomas Harte
5a87506f3d Fix Bcc, making decision that add_pc is relative to start of instruction. 2022-05-03 15:21:42 -04:00
Thomas Harte
90f0005cf2 Proceed to failing Bcc and flagging up my lack of an implementation for BSR. 2022-05-03 14:45:49 -04:00
Thomas Harte
d8b3748d24 Fix Scc size, DBcc behaviour. 2022-05-03 14:40:51 -04:00
Thomas Harte
b6ffff5bbd Distinguish [ADD/SUB]QA from [ADD/SUB]Q. 2022-05-03 14:17:26 -04:00
Thomas Harte
5ebae85a16 Start recording successes. 2022-05-03 11:28:50 -04:00
Thomas Harte
b3cf13775b Consume operand_flags into Instruction.hpp. 2022-05-03 11:09:57 -04:00
Thomas Harte
2f2d6bc08b Correct CMPw. 2022-05-03 09:05:34 -04:00
Thomas Harte
fc9a35dd04 Test add/sub, add an exception for invalid Sequences. 2022-05-02 20:09:38 -04:00
Thomas Harte
3827ecd6d3 Proceed to complete test running. 2022-05-02 12:57:45 -04:00
Thomas Harte
14532867a4 Sneaks towards testing EXT. 2022-05-02 08:00:56 -04:00
Thomas Harte
56fe00c5fb Correct errors preparatory to Executor's lack of flow controller actions. 2022-05-01 20:40:57 -04:00
C.W. Betts
5758693b7d Minor pokes to the test files code. 2021-03-19 02:19:49 -06:00
Thomas Harte
8641494809 Resolve various test-case warnings. 2020-09-27 15:10:29 -04:00
Thomas Harte
851cba0b25 Corrects lambda capture. 2020-02-22 12:34:16 -05:00
Thomas Harte
9ca2d8f9f2 Tried to be less lazy with lambda captures. 
This is primarily defensive.
 2020-02-14 23:39:08 -05:00
Thomas Harte
a28c52c250 Fixes A7-relative JSRs. 
I completely withdraw my earlier statement re: the test cases.
 2020-01-04 22:22:33 -05:00
Thomas Harte
cb7d6c185c Further expands test coverage. 2020-01-01 20:00:37 -05:00
Thomas Harte
5be30b1f7b Introduces further comparative tests, prompting a new CHK fix. 
Specifically: how to set N when both is_under and is_over are true, and to eliminate a failure fully to prefetch in the longer addressing modes.
 2020-01-01 19:11:36 -05:00
Thomas Harte
d26ce65236 Introduces an RTR test. 2019-12-25 19:50:12 -05:00
Thomas Harte
9464658d1e Adds a count summary. 2019-12-17 22:19:23 -05:00
Thomas Harte
60a9b260b1 Corrects collection of instruction codes. 2019-12-16 00:01:18 -05:00
Thomas Harte
e603fc6aaa Simplifies failure output for me. 2019-12-15 21:26:47 -05:00
Thomas Harte
1bf4686c59 Adds plentiful additional tests. Though still only a fraction of the anticipated total. 2019-12-14 22:58:51 -05:00
Thomas Harte
a500fbcd73 Expands tests to most of ORI, EORI, ANDI, ADDI and SUBI. 2019-12-14 22:23:40 -05:00
Thomas Harte
d0ef41f11e Adds a temporary manual escape clause for testing specific features. 2019-12-14 21:40:21 -05:00
Thomas Harte
adf6723bf6 Ensures state is evaluated directly at opcode end. 2019-12-14 15:09:06 -05:00