Thomas Harte
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0d1231980a
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Advanced to getting specific warnings in the ed-page table. So that's progress.
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2017-06-18 17:25:15 -04:00 |
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Thomas Harte
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82a015892b
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Started adapting to the newly-segmented world.
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2017-06-18 17:18:01 -04:00 |
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Thomas Harte
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194b7f60c5
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Rephrased to allow non-conditional waits; expanded macros to cover all permitted lengths of read and write.
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2017-06-18 17:08:50 -04:00 |
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Thomas Harte
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ebc7356db5
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Reformulated the machine cycle slightly to support posting operation plus phase, thereby exposing the segue points at which waits might be inserted. So: to stick to the rule that CPUs expose the minimum amount of information sufficient completely to reconstruct bus activity. This breaks the Z80 for now.
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2017-06-18 12:21:27 -04:00 |
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Thomas Harte
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e1a2580b2a
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Renamed BusOperation to MachineCycle::Operation.
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2017-06-17 21:53:45 -04:00 |
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Thomas Harte
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efc7f9df37
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Combined I and R into a register pair.
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2017-06-17 18:18:28 -04:00 |
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Thomas Harte
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aed2827e7b
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Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
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2017-06-12 22:22:00 -04:00 |
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Thomas Harte
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b9dbb6bcf8
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Discovered my timing error: the I/R <-> A loads should take an extra cycle. This means the ZX80 now finally takes the correct 207 cycles per line. Fixed the video output wave to be clocked at the appropriate rate.
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2017-06-12 18:55:04 -04:00 |
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Thomas Harte
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d12e50eb02
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Corrected "should I adjust history?" tests.
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2017-06-11 16:41:34 -04:00 |
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Thomas Harte
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db30f53ab0
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Added the capacity to back-date interrupt line changes within a machine cycle, so that machines which time themselves entirely within perform_machine_cycle can still be cycle accurate on those changes.
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2017-06-11 13:31:02 -04:00 |
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Thomas Harte
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b55579c348
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Fixed usage of flush: the subclass version is definitively used.
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2017-06-06 17:52:44 -04:00 |
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Thomas Harte
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3df6eba237
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Fixed: my HALT line wasn't actually halting. NOPs followed, but the PC just kept counting.
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2017-06-05 10:35:03 -04:00 |
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Thomas Harte
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e940e02126
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Added a short circuit to set_interrupt_line, mostly to make breakpoints slightly more convenient to place.
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2017-06-05 09:37:19 -04:00 |
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Thomas Harte
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7f743c6fb0
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Got explicit about permitted type conversions.
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2017-06-04 18:40:59 -04:00 |
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Thomas Harte
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096551ab3e
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Made a first attempt to hash out the ZX80's bus. Video output isn't yet going though. Can't seem to find clarity on whether horizontal sync is really programmatic. Let's see.
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2017-06-04 18:32:23 -04:00 |
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Thomas Harte
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c485c460f7
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Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.
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2017-06-04 18:08:35 -04:00 |
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Thomas Harte
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d2637123c4
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Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.
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2017-06-04 17:55:19 -04:00 |
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Thomas Harte
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0eebfdb4cc
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Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.
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2017-06-04 15:39:37 -04:00 |
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Thomas Harte
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7811374b0f
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Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).
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2017-06-04 15:07:07 -04:00 |
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Thomas Harte
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a2f01b4a46
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Corrected CPx bit 3 and 5 flags. I think only BIT n, (HL) with the famous MEMPTR reliance is preventing a complete pass by Zexall now.
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2017-06-04 14:59:18 -04:00 |
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Thomas Harte
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f5c910beb7
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Fixed LDIR/LDDR bit 3/5 flags. This seems once again to satisfy FUSE.
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2017-06-04 14:18:04 -04:00 |
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Thomas Harte
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4e014ca748
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Ensured BIT takes bits 5 and 3 from the computed address if used on indexed pages. That seems to cover 97 failures out of 100?
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2017-06-04 14:13:38 -04:00 |
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Thomas Harte
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1a811b1ab1
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Eliminated the function call inherent to every decode, and also moved the fixed table of operations into a non-templated base class.
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2017-06-03 22:19:35 -04:00 |
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Thomas Harte
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c26349624c
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This, of course, should be inline to gain any benefit from the slightly-tortured private implementation.
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2017-06-03 22:00:57 -04:00 |
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Thomas Harte
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b642d9f712
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Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.
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2017-06-03 21:54:42 -04:00 |
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Thomas Harte
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fd6623b5a5
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Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
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2017-06-03 21:22:16 -04:00 |
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Thomas Harte
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b304c3a4b9
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Eliminated the 6502's reliance on the micro-op scheduler.
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2017-06-03 20:30:07 -04:00 |
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Thomas Harte
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3ceef2005b
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Pulled the Z80 from the MicroOpScheduler inheritance tree as it barely uses the thing, and that allows me to make the MicroOp structure private.
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2017-06-03 19:17:34 -04:00 |
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Thomas Harte
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24c84ca6f5
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Commented out as-yet-unimplemented features.
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2017-06-03 19:10:23 -04:00 |
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Thomas Harte
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7898f643ac
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Added bus request/acknowledge logic.
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2017-06-03 19:09:47 -04:00 |
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Thomas Harte
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7bd45d308a
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Error was simply failure of the interrupt-mode setter. Fixed.
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2017-06-03 18:58:13 -04:00 |
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Thomas Harte
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b3da16911f
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Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.
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2017-06-03 18:42:54 -04:00 |
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Thomas Harte
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8c41a0f0ed
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Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.
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2017-06-03 17:53:44 -04:00 |
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Thomas Harte
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3e9212aaff
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Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
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2017-06-03 17:41:45 -04:00 |
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Thomas Harte
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a2ec902773
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Made an attempt at implementing all three modes of IRQ.
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2017-06-03 17:07:05 -04:00 |
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Thomas Harte
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1c0130fd02
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Cleaned up with a macro, and decided to make absolutely sure that DecodeOperation is functioning as intended by removing the MoveToNextProgram from fetch-decode-execute.
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2017-06-03 12:19:25 -04:00 |
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Thomas Harte
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3e3d6f97f4
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Edged towards being able to implement interrupt mode 0: created a special-case micro-op for incrementing the PC, and formalised that DecodeOperation is a terminal operation.
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2017-06-03 12:16:21 -04:00 |
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Thomas Harte
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9c3bda0111
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Attempted to round out NMI handling.
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2017-06-03 11:30:12 -04:00 |
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Thomas Harte
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d14902700a
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Minor syntax and wiring fixes.
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2017-06-01 22:33:05 -04:00 |
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Thomas Harte
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c95c32a9fe
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Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.
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2017-06-01 22:31:04 -04:00 |
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Thomas Harte
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35e045d7a7
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Made a first attempt at the correct segue into the three main kinds of interrupt, though the programs aren't written yet. So undefined behaviour would abound were an interrupt to occur. But it lets me figure out what effect the check has on performance. I hope little.
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2017-06-01 22:16:22 -04:00 |
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Thomas Harte
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084e1f3d51
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Added a latching of interrupt status before each bus operation, and reset and power-on inputs.
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2017-06-01 21:40:08 -04:00 |
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Thomas Harte
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5b43cefb85
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Started filling an appropriate mask variable with the interrupt request status right now. Which is step one towards implementing interrupts.
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2017-06-01 20:34:52 -04:00 |
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Thomas Harte
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aab637c9e7
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Made check_address_for_trap inlineable.
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2017-06-01 18:28:34 -04:00 |
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Thomas Harte
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7d9b197383
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Pulled the .get() call for fetch-decode-execute out of the main loop.
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2017-06-01 18:28:04 -04:00 |
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Thomas Harte
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c9dd267ec1
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Sketched an interface for signalling interrupts and pulled out some of the repetition in flag setting from ADD/ADC/SUB/SBC/CP.
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2017-05-31 22:51:32 -04:00 |
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Thomas Harte
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a5254989f8
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Rewired the Z80 not to use the program queue, as it's not proven a useful abstraction in practice and doing so yields an immediate 22% speed increase.
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2017-05-31 20:15:56 -04:00 |
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Thomas Harte
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494ce073b5
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Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging.
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2017-05-31 19:58:57 -04:00 |
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Thomas Harte
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b99e4210ba
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Eliminated pointless abstraction; I ended up going indirect on instruction pages rather than scheduling methods.
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2017-05-31 19:57:03 -04:00 |
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Thomas Harte
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d3b74cbc91
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Set proper initial value for number_of_cycles_.
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2017-05-31 19:55:51 -04:00 |
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