743 Commits

Author	SHA1	Message	Date
Thomas Harte	e1a2580b2a	Renamed BusOperation to MachineCycle::Operation.	2017-06-17 21:53:45 -04:00
Thomas Harte	08a542a324	Reenabled the fast-loading hack.	2017-06-15 18:30:12 -04:00
Thomas Harte	9b3d05e05f	Simplified decoding logic.	2017-06-14 22:24:44 -04:00
Thomas Harte	d8e3103a2b	Fixes: switched ZX80 and ZX81 timing to the correct way around, ensured that my wait takes effect if HALT **isn't** set, and made sure to recover from it.	2017-06-13 21:48:17 -04:00
Thomas Harte	76a64d13a0	Made a first attempt at ZX81 emulation.	2017-06-13 21:25:55 -04:00
Thomas Harte	1e975859c2	Started splitting ZX80 and ZX81 paths. Also the '80 fires its horizontal sync a little earlier than the '81, so pulled that back a little.	2017-06-13 20:09:09 -04:00
Thomas Harte	4c5261bfa0	Made first attempt to use the horizontal counter for something; here for sync timing only, even though I've gone exclusively with '81-style timing for now.	2017-06-12 22:28:30 -04:00
Thomas Harte	8b09b4180b	This now at least remembers whether it is meant to be a ZX81 and has storage for a horizontal counter.	2017-06-12 21:33:16 -04:00
Thomas Harte	b9dbb6bcf8	Discovered my timing error: the I/R <-> A loads should take an extra cycle. This means the ZX80 now finally takes the correct 207 cycles per line. Fixed the video output wave to be clocked at the appropriate rate.	2017-06-12 18:55:04 -04:00
Thomas Harte	302c2e94de	Corrected lingering hard-coded mask. So titles for memory configurations above 1kb now load.	2017-06-11 21:27:46 -04:00
Thomas Harte	06fe07932a	While tidying up, killed an unused instance variable.	2017-06-11 21:21:26 -04:00
Thomas Harte	6913c7a018	This also can just use rom_mask_.	2017-06-11 19:29:20 -04:00
Thomas Harte	6b602c74b7	Made an attempt to support memory maps other than the unexpanded default of 1kb.	2017-06-11 19:29:02 -04:00
Thomas Harte	e40d553045	Bumped the tape parser up into the machine to ensure a maintained state. Temporarily disabled normally-timed tape playback.	2017-06-11 18:31:43 -04:00
Thomas Harte	e5b30cdfbb	Attempted to ensure appropriate resumption of processing after quick-reading a tape byte.	2017-06-11 17:28:47 -04:00
Thomas Harte	ba5f34f827	Narrowed view to the centre 80% of a frame.	2017-06-11 17:24:32 -04:00
Thomas Harte	84d2feb2e6	Cleaned up and implemented fast-tape hack. I've decided it'd be better to test some other software, potentially to give multiple issues to think about, rather than sitting around with just the one.	2017-06-11 16:42:49 -04:00
Thomas Harte	d910a4fd38	Adjusted to signal an interrupt during the refresh cycle rather than weirdly just afterwards. Which cuts video timing down by 4 cycles a line. There still might be a problem here somewhere though, as I'm getting 206 cycles/line and the internet states it should be 207. ... Also: lots of printfs have grown temporarily as I try to figure out what I'm doing so wrong as to break loading.	2017-06-11 13:32:20 -04:00
Thomas Harte	5626d35bc4	Tried flipping the bit meaning; decided at least to leave it in full-byte form.	2017-06-06 18:38:05 -04:00
Thomas Harte	63e0802f4e	Ensured tape input appears on the returned value.	2017-06-06 18:16:27 -04:00
Thomas Harte	e3ee9604a5	Added comments.	2017-06-06 18:01:33 -04:00
Thomas Harte	8c66e1d99d	Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data.	2017-06-06 17:53:23 -04:00
Thomas Harte	ca9e8aecd6	Made a seemingly unsuccessful attempt to add tape input.	2017-06-06 10:13:32 -04:00
Thomas Harte	cc4cb45e9d	Implemented keyboard input and ensured that the signal generated is marked as composite, putting the colour-suppression ball into the CRT's court.	2017-06-06 09:25:18 -04:00
Thomas Harte	ebbf6e6133	Surprisingly, I think this may actually be the correct output: stopped throwing away the I part of the refresh register and flipped black and white.	2017-06-06 09:03:09 -04:00
Thomas Harte	cba07dec7e	Doubled up to display all eight pixels. To confirm that they are the wrong pixels.	2017-06-06 08:59:00 -04:00
Thomas Harte	6f7037b2b1	Made an initial stab at outputting half the correct pixels.	2017-06-06 08:55:07 -04:00
Thomas Harte	ef4b2f963d	Probably more-or-less corrected. But this is all a bit too interdependent.	2017-06-05 23:52:56 -04:00
Thomas Harte	97f3ff03b6	Restored white background and attempted to correct output timing deficiencies. Incomplete success.	2017-06-05 23:50:04 -04:00
Thomas Harte	2fbc7a2869	Made a very basic attempt at getting something that at least demarcates proper graphics output.	2017-06-05 23:32:49 -04:00
Thomas Harte	4983718df7	Got to outputting something to the CRT. Should be just proper syncs and a paper background. It's not synchronising properly, so something is amiss in my timing.	2017-06-05 10:47:42 -04:00
Thomas Harte	23ca00fd9a	Added memory fuzzing as a way to verify state being written by the Z80. Eventually discovered the HALT problem as fixed in the last commit, so have stripped away the caveman stuff again.	2017-06-05 10:36:07 -04:00
Thomas Harte	893f61b490	Attempted specifically to reproduce the 1kb ZX80 memory map in the hope of getting compact lines and in case mirroring is why I'm getting completely empty video reads. Still no action.	2017-06-05 09:38:49 -04:00
Thomas Harte	7e3a46c33e	[Re]discovered that sync may also be a product of the interrupt cycle. So started looking into that.	2017-06-04 21:54:55 -04:00
Thomas Harte	73654d51dd	Wired up actually to run.	2017-06-04 18:37:13 -04:00
Thomas Harte	096551ab3e	Made a first attempt to hash out the ZX80's bus. Video output isn't yet going though. Can't seem to find clarity on whether horizontal sync is really programmatic. Let's see.	2017-06-04 18:32:23 -04:00
Thomas Harte	c485c460f7	Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.	2017-06-04 18:08:35 -04:00
Thomas Harte	d2637123c4	Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.	2017-06-04 17:55:19 -04:00
Thomas Harte	2562306802	Merge branch 'master' into Z80	2017-05-16 21:05:00 -04:00
Thomas Harte	2ee8a7056e	Corrected TIA no longer to assume phase is an automatic quarter askew.	2017-05-16 20:43:28 -04:00
Thomas Harte	a5075d9eb5	Formalised the reasoning behind the colour phase fix-up and made it an opt-in per-caller value. Only the Oric currently needs to opt in.	2017-05-16 20:31:39 -04:00
Thomas Harte	eb8a2de5d6	Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.	2017-05-15 07:38:59 -04:00
Thomas Harte	0808e9b6fb	Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.	2017-05-14 22:08:15 -04:00
Thomas Harte	8e35e913bb	Formally withdrew the 'load automatically' option for the Vic, having removed that option elsewhere.	2017-05-14 16:59:24 -04:00
Thomas Harte	5d91a2600d	Permitted ROM-style PRGs that are not a power-of-two in size, and added extra safety checks on loading data from a tape.	2017-05-08 22:15:35 -04:00
Thomas Harte	cb66c7e2dc	Performed some minor tidying.	2017-05-08 21:05:35 -04:00
Thomas Harte	61f8f2f18c	Switched to a more straightforward way of exiting from tape data loading.	2017-05-08 20:58:55 -04:00
Thomas Harte	7b43ae0a92	Implemented a catch for loading the data portion of files.	2017-05-07 22:22:59 -04:00
Thomas Harte	2807e3134f	Implemented speedy header finding. So that's half of it.	2017-05-07 20:32:48 -04:00
Thomas Harte	0771363f3b	Removed one piece of unnecessary logging.	2017-05-06 22:22:03 -04:00