Thomas Harte
|
4909325e79
|
Implemented read deleted data.
|
2017-08-12 13:01:17 -04:00 |
|
Thomas Harte
|
a4ee697ed1
|
Quickie: head unload is scheduled only if the head is presently loaded.
|
2017-08-12 12:53:45 -04:00 |
|
Thomas Harte
|
0f15a2f97f
|
Relented: it actually looks like status bytes aren't per-drive. But each drive may fail at seeking individually. So that piece of state accumulates at the 8272 drive.
|
2017-08-12 12:52:36 -04:00 |
|
Thomas Harte
|
89ace671a4
|
Corrected unload time. Was 8000 times too short.
|
2017-08-12 09:44:01 -04:00 |
|
Thomas Harte
|
e7db2a2f6d
|
Sought to introduce head loading and unloading delays.
|
2017-08-12 09:36:21 -04:00 |
|
Thomas Harte
|
ffb1a14ace
|
Minor: clear status registers before a read data.
|
2017-08-11 18:56:33 -04:00 |
|
Thomas Harte
|
e4f04d0977
|
Merge branch 'master' into AYFidelity
|
2017-08-11 14:41:08 -04:00 |
|
Thomas Harte
|
a5593bec79
|
Threw in support for the light-pen trigger.
|
2017-08-10 15:00:14 -04:00 |
|
Thomas Harte
|
a1e2646301
|
Imposed counter size limits.
|
2017-08-10 14:58:24 -04:00 |
|
Thomas Harte
|
6a6e5ae79c
|
Forced users of the 6845 to be explicit about which type. So far with no effect.
|
2017-08-10 12:28:57 -04:00 |
|
Thomas Harte
|
02d792c003
|
Simplified logic slightly, avoiding repetition.
|
2017-08-10 11:48:37 -04:00 |
|
Thomas Harte
|
be8e7a4144
|
Eliminated false register aliasing, restricted register sizes and locked out reading and writing where appropriate.
|
2017-08-10 11:22:30 -04:00 |
|
Thomas Harte
|
b1dbd7833a
|
Merge branch 'master' into 6845Address
|
2017-08-10 11:15:08 -04:00 |
|
Thomas Harte
|
a4c910f1de
|
This appears to be a more accurate take on 6845 address advancement — it is necessary that character output has finished for the line address to be updated.
|
2017-08-10 11:12:53 -04:00 |
|
Thomas Harte
|
2eed24e859
|
Made an initial attempt at [a subset of] multi-sector reads.
|
2017-08-10 11:11:26 -04:00 |
|
Thomas Harte
|
b11d142cff
|
Switched to descriptive names.
|
2017-08-08 20:35:41 -04:00 |
|
Thomas Harte
|
021ff8674e
|
Added something for sense drive status.
|
2017-08-08 20:30:54 -04:00 |
|
Thomas Harte
|
e3d1f4fe1e
|
Subjectively, this might be more correct. It definitely prevents intermediate frequencies. More research required.
|
2017-08-08 17:58:35 -04:00 |
|
Thomas Harte
|
3bdedfd749
|
Improved comments.
|
2017-08-08 07:44:46 -04:00 |
|
Thomas Harte
|
46278ff297
|
Experimental: is this meant to be a compare-before-increment?
|
2017-08-07 23:02:29 -04:00 |
|
Thomas Harte
|
390ecec3d9
|
Added: now declines to pass on output if in input mode for ports A and B.
|
2017-08-07 19:56:22 -04:00 |
|
Thomas Harte
|
41a30c147d
|
Adjusted: invalid register selection simply deselects all registers.
|
2017-08-07 19:51:36 -04:00 |
|
Thomas Harte
|
4709ae80cb
|
Added port direction tests.
|
2017-08-07 19:36:55 -04:00 |
|
Thomas Harte
|
7fbb455836
|
Per the CPC test I'm checking, 0s should be returned for non-retained bits, not 1s.
|
2017-08-07 19:07:12 -04:00 |
|
Thomas Harte
|
745afd217f
|
The port input/output flags are now honoured; reading a port that is set as an output returns the current output value.
|
2017-08-07 19:01:18 -04:00 |
|
Thomas Harte
|
47732ffb98
|
Prevented the 8272 from overreading ID fields (and, by doing so, overrunning its internal buffer). Exposed the MFMController's CRC generator for inspection.
|
2017-08-07 12:37:22 -04:00 |
|
Thomas Harte
|
d07f3216ab
|
Added a broad phase on whether seeking is ongoing.
|
2017-08-07 12:12:59 -04:00 |
|
Thomas Harte
|
68c73184b1
|
Had failed to spot that by taking control of stepping at this level, the appropriate invalidate_tracks were not being sent.
|
2017-08-07 10:36:53 -04:00 |
|
Thomas Harte
|
7f824d6494
|
Ensured seeks and recalibrates end immediately if no seeking is required.
|
2017-08-07 10:31:32 -04:00 |
|
Thomas Harte
|
3219212f03
|
A closer inspection of the data sheet seems to suggest that invalid command sequences will post ST0.
|
2017-08-07 07:35:41 -04:00 |
|
Thomas Harte
|
d90e35e5bd
|
Added a bunch of comments, and ensured that the data request bit remains set for the entire period that command bytes are accepted.
|
2017-08-07 07:27:00 -04:00 |
|
Thomas Harte
|
73f8488150
|
Reaching the end of the usable part of my day, decided to tidy up a little before bed with indentation that reflects a distinction between top-level entry points and mere loops.
|
2017-08-06 22:14:18 -04:00 |
|
Thomas Harte
|
3853966a1e
|
Removed formal storage of ST3, as it just seems to be composed live. This may turn out also to be the best way to deal with ST0–2, time will tell. Also took a stab at the error in responding properly to the ROM's intended use of seek might be accepting new commands as replacements for old ones rather than rejecting them. That didn't seem to do the trick.
|
2017-08-06 22:10:12 -04:00 |
|
Thomas Harte
|
d63893a437
|
Collapsed implementations of recalibrate and seek, and decided to intend to go for an upward count on steps taken rather than a downward one. But seek continues presently to fail.
|
2017-08-06 21:52:52 -04:00 |
|
Thomas Harte
|
90c74043f5
|
Remembered to toggle off RQM between bytes. CAT now works.
|
2017-08-06 21:21:59 -04:00 |
|
Thomas Harte
|
600445d90a
|
Made a first attempt to return sector contents.
|
2017-08-06 20:40:29 -04:00 |
|
Thomas Harte
|
e4b405fd3d
|
With the ROM now using a read ID to set its expectations, implemented that and fixed FIND/READ_HEADER macros for multiple use. Execution now reaches the unimplemented section of read data.
|
2017-08-06 20:32:46 -04:00 |
|
Thomas Harte
|
3b7ecbdf0d
|
Renamed result_ to result_stack_ to emphasis the fact that it goes backwards. Switched meaning of CB so that it is set for the entire command, execution and result phases.
|
2017-08-06 20:17:12 -04:00 |
|
Thomas Harte
|
01efb645cb
|
Took a reasonable gamble that the CHRN reported is from internal registers, not from the last-found header.
|
2017-08-06 19:57:34 -04:00 |
|
Thomas Harte
|
b5ec1f42d5
|
Started resetting 'busy' when entering the result phase. AMSDOS now complains of a missing disk after failing to find sector 01. My belief is that it should end up asking for C1. So this is not even getting through a failure to find a sector correctly yet.
|
2017-08-06 19:48:17 -04:00 |
|
Thomas Harte
|
e9972aa0dd
|
Added respect for the index-hole limit on reading, and an error phase.
|
2017-08-06 19:25:44 -04:00 |
|
Thomas Harte
|
1c9a744b01
|
Made an effort to start inspecting ID fields, at least. Discovered that my emulation has somehow stopped proceeding beyond sense interrupt status though. Fix one in that area: adjust ST0 just in time for the sense interrupt status response, as that'll need to specify the drive number properly.
|
2017-08-06 18:06:20 -04:00 |
|
Thomas Harte
|
e6d4bb29d8
|
Discovered correct sense interrupt status result if nobody is in the completed seeking state, and switched to it. It's a single 0x80 rather than two bytes.
|
2017-08-06 15:34:33 -04:00 |
|
Thomas Harte
|
6c5b562d97
|
Made an attempt at some of the correct seek/recalibrate behaviour: it's now asynchronous from command processing and able to work on up to four drives at once. I just probably am not yet hitting all the status flags I need to hit.
|
2017-08-06 15:22:07 -04:00 |
|
Thomas Harte
|
a7103f9333
|
Disks are now communicated to the 8272. Which is able to handle four of them.
|
2017-08-06 13:24:14 -04:00 |
|
Thomas Harte
|
c12425e141
|
Added storage for the extended four status registers, and made an attempt at implementing the two most trivial result-phase commands. Am slightly paused momentarily trying to figure out whether seek activity is orthogonal to read/write activity.
|
2017-08-06 12:55:57 -04:00 |
|
Thomas Harte
|
89f6de1383
|
Started on a real ugly-implementation coroutine approach, and implemented specify as a fairly trivial first command: it has no result phase, and is the only thing called by AMSDOS as part of the initialisation sequence.
|
2017-08-06 12:36:18 -04:00 |
|
Thomas Harte
|
34eaf75352
|
Fixed WAIT_FOR_TIME macro.
|
2017-08-06 12:08:54 -04:00 |
|
Thomas Harte
|
29288b690e
|
Switched disk controllers to be instantiated explicitly in terms of cycles, created an Amstrad-specific subclass of the 8272 to record the direct programmatic availability of all disk motors bundled together, and otherwise adjusted to ensure the thing is clocked and that the motor is enabled and disabled appropriately. The 8272 is also now formally a subclass of the incoming MDM controller.
|
2017-08-06 09:45:16 -04:00 |
|
Thomas Harte
|
25fd3f7e50
|
Mildly increased work in here, still primarily oriented towards logging what I actually need to get done.
|
2017-08-05 22:26:59 -04:00 |
|
Thomas Harte
|
3e984e75b6
|
Strung up an empty shell that eventually should contain the 8272, and added appropriate IO decoding to the Amstrad.
|
2017-08-05 19:45:52 -04:00 |
|
Thomas Harte
|
26ce6cdab2
|
Permitted register 3 to dictate vertical sync length.
|
2017-08-04 08:56:36 -04:00 |
|
Thomas Harte
|
3ca9c38777
|
Attempted to move to more accurate bus reading — if control lines are set then all subsequent data inputs should act according to the current control lines; changes to port input should be reflected live upon readings, etc.
|
2017-08-02 19:45:58 -04:00 |
|
Thomas Harte
|
0267bc237f
|
Added the ability to set a port input, and relaxed bus state testing. I think my on-demand bus reactions here are inappropriate, so more work to do here probably.
|
2017-08-01 18:04:51 -04:00 |
|
Thomas Harte
|
e6854ff8db
|
Corrected typo: the input to an AY is BDIR, not BCDIR.
|
2017-08-01 17:06:57 -04:00 |
|
Thomas Harte
|
2d4e202be3
|
Completed dangling comment.
|
2017-08-01 17:01:36 -04:00 |
|
Thomas Harte
|
64da8e17d1
|
Fixed: of course this should take a reference to an existing port handler rather than hatching its own; otherwise additional communication with a port handler by an i8255 owner doesn't work as intended.
|
2017-08-01 17:01:20 -04:00 |
|
Thomas Harte
|
08ad35efd9
|
It's barely an implementation of the 8255, but ensured that data is bounced into the PortHandler, conveniently assuming the interaction mode used by the CPC.
|
2017-08-01 16:34:13 -04:00 |
|
Thomas Harte
|
58b98267fc
|
Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.
|
2017-08-01 16:15:19 -04:00 |
|
Thomas Harte
|
ace71280a0
|
Removed implementation file; this is only ever going to be a template.
|
2017-08-01 16:00:17 -04:00 |
|
Thomas Harte
|
1d99c116e7
|
Actually, this is probably more correct: increment and then compare, but increment the refresh address once more after the final character, to avoid repeating it.
|
2017-08-01 15:29:37 -04:00 |
|
Thomas Harte
|
ee27e16fb1
|
Switched to post-tests increment. Seems to give proper screen width, but also eliminates that 'compare to +1' step that felt unlikely.
|
2017-08-01 15:19:25 -04:00 |
|
Thomas Harte
|
3b1db14817
|
Made a quick attempt at properly updating the refresh address.
|
2017-08-01 07:36:03 -04:00 |
|
Thomas Harte
|
e3f677fa37
|
I was under-counting row lines. Adjusted comparison. The emulator now produces a solid white square of approximately correct proportions. I'm sure that filling in pixels will reveal the next set of bugs.
|
2017-07-31 22:21:46 -04:00 |
|
Thomas Harte
|
5c68b6cc21
|
Fixed display enable reset when there's no adjustment area. A practical lesson in failure to factor.
|
2017-07-31 22:16:08 -04:00 |
|
Thomas Harte
|
ffaa627820
|
Fixed frame restart when there is no adjustment period.
|
2017-07-31 22:13:45 -04:00 |
|
Thomas Harte
|
5a396f6787
|
Added an explicit cast.
|
2017-07-31 22:04:31 -04:00 |
|
Thomas Harte
|
cb0dc7b434
|
I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.
|
2017-07-31 22:01:54 -04:00 |
|
Thomas Harte
|
e28829bd1b
|
Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
|
2017-07-31 20:14:46 -04:00 |
|
Thomas Harte
|
68ceeab610
|
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
|
2017-07-31 19:56:59 -04:00 |
|
Thomas Harte
|
4abd62e62b
|
Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
|
2017-07-27 22:05:29 -04:00 |
|
Thomas Harte
|
1da24d10fd
|
Corrected a couple of build errors.
|
2017-07-27 08:05:14 -04:00 |
|
Thomas Harte
|
8361756dc4
|
Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
|
2017-07-27 07:40:02 -04:00 |
|
Thomas Harte
|
1c2f68f129
|
Removed, as it's been relocated.
|
2017-07-25 20:43:05 -04:00 |
|
Thomas Harte
|
75d67ee770
|
Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
|
2017-07-25 20:20:55 -04:00 |
|
Thomas Harte
|
a1e9a54765
|
Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
|
2017-07-25 20:09:13 -04:00 |
|
Thomas Harte
|
545683df6f
|
Added some documentation, got explicit again about cycle/half-cycle intermingling, and added flush as what amounts to divide(1), for cleaner usage without a clock divider.
|
2017-07-25 19:50:40 -04:00 |
|
Thomas Harte
|
cfbd62a5dc
|
Attempted to fix implementation of divide, and marked everything as-yet unmarked as inline.
|
2017-07-25 07:43:39 -04:00 |
|
Thomas Harte
|
40339a12e1
|
Formalised the use of a cycles count with a divider, bringing a few additional plain-int users into the fold.
|
2017-07-25 07:15:31 -04:00 |
|
Thomas Harte
|
9be9bd9106
|
Neatened layout.
|
2017-07-24 22:52:35 -04:00 |
|
Thomas Harte
|
c1527cc9e2
|
Reduced back-and-forth between Cycles and ints within the Oric.
|
2017-07-24 22:46:31 -04:00 |
|
Thomas Harte
|
a1a3aab115
|
Fixed implicit sign conversion.
|
2017-07-24 22:40:15 -04:00 |
|
Thomas Harte
|
c77a83d86f
|
The 6560 is now a ClockReceiver. This reduces to zero the number of remaining instances of the text run_for_cycles in this codebase.
|
2017-07-24 22:38:35 -04:00 |
|
Thomas Harte
|
efdac2ce8c
|
The 6522 is now a ClockReceiver.
|
2017-07-24 22:29:09 -04:00 |
|
Thomas Harte
|
2912d7055b
|
The 6532 is now a ClockReceiver.
|
2017-07-24 21:57:24 -04:00 |
|
Thomas Harte
|
b7f88e8f61
|
Filter is now a ClockReciever, affecting all sound output devices.
|
2017-07-24 21:29:13 -04:00 |
|
Thomas Harte
|
8a2bdb8d22
|
Converted the TimedEventLoop and the things that sit atop it into ClockReceivers.
|
2017-07-24 21:19:05 -04:00 |
|
Thomas Harte
|
b82bef95f3
|
Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
|
2017-07-24 20:10:05 -04:00 |
|
Thomas Harte
|
8a0b0cb3d7
|
Extended both classes to allow copy assignment, copy construction and implicit zero-length construction.
|
2017-07-23 22:13:41 -04:00 |
|
Thomas Harte
|
1ba3f262a2
|
Sketched out a template for clock-receiving components to allow them to be implemented in terms of either half or whole cycles.
|
2017-07-22 21:46:50 -04:00 |
|
Thomas Harte
|
8755824c64
|
Added some documentation.
|
2017-07-22 17:25:53 -04:00 |
|
Thomas Harte
|
64865b3f41
|
Signedness fixes.
|
2017-07-21 21:23:34 -04:00 |
|
Thomas Harte
|
53f0e1896b
|
Made delay_time_ unsigned for safe comparison.
|
2017-07-21 21:21:23 -04:00 |
|
Thomas Harte
|
aaa60dab12
|
Fixed signedness of index.
|
2017-07-21 21:21:01 -04:00 |
|
Thomas Harte
|
12f7e1b804
|
Enshrined a default colour burst amplitude. Which now everybody relies on. The 102 figure is derived from the burst apparently being 40 IRE.
|
2017-07-07 23:35:14 -04:00 |
|
Thomas Harte
|
eb8a2de5d6
|
Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.
|
2017-05-15 07:38:59 -04:00 |
|
Thomas Harte
|
e270b726b3
|
Tweaked blue, increased saturation.
|
2017-05-13 22:01:02 -04:00 |
|
Thomas Harte
|
44ce7fa54c
|
Corrected luminances across the board, and PAL colours.
|
2017-05-13 21:50:09 -04:00 |
|
Thomas Harte
|
b0142cf050
|
Made an updated stab at NTSC colours.
|
2017-05-13 14:29:36 -04:00 |
|
Thomas Harte
|
a340331229
|
Introduced 1-bit of saturation, returning black and white as black and white.
|
2017-05-11 21:31:58 -04:00 |
|
Thomas Harte
|
15d17c12d5
|
Switched the 6560 to two bytes per pixel, since one isn't sufficient for precision and because mixing up the implementation might help me to figure out what's amiss.
|
2017-05-09 21:22:01 -04:00 |
|
Thomas Harte
|
5998123868
|
Added some consts, for a minor safety improvement.
|
2017-05-06 19:53:24 -04:00 |
|
Thomas Harte
|
e01f3f06c8
|
Completed curly bracket movement.
|
2017-03-26 14:34:47 -04:00 |
|
Thomas Harte
|
a4c5eebd1e
|
The latest Atari Age-discovered numbers suggest this starts up in 1024T mode.
|
2017-03-21 18:22:50 -04:00 |
|
Thomas Harte
|
c445eaec3e
|
Switched startup values, following a comment on AtariAge. May or may not be correct, the thread was speculative.
|
2017-03-19 17:38:26 -04:00 |
|
Thomas Harte
|
e0bca1e37b
|
Reinstated the 16 and 32 kb Atari pagers, and ensured the 6532 always starts in a valid state.
|
2017-03-18 17:34:34 -04:00 |
|
Thomas Harte
|
d3257c345a
|
Tested against public ROMs and corrected. Also moved the deferred adjustment into a more canonical place.
|
2017-03-04 17:00:28 -05:00 |
|
Thomas Harte
|
e09b76bf32
|
Fixed 'same value, then immediate increment, then proper counting increments' behaviour and ensured it takes one cycle to commit a value. Adjusted tests to match.
|
2017-03-04 15:57:54 -05:00 |
|
Thomas Harte
|
ced644b103
|
It seems likely that an AY divides its clock by 8, not 16. I had conflated wave frequency and counter clock.
|
2017-01-11 22:03:01 -05:00 |
|
Thomas Harte
|
eca3995481
|
Added a CRC check for read address, ensured CRC, lost data and record not found are initially reset.
|
2017-01-01 21:00:25 -05:00 |
|
Thomas Harte
|
044c920a5b
|
Made it more explicit that there are no unhandled cases.
|
2017-01-01 20:56:52 -05:00 |
|
Thomas Harte
|
0df9ce5a76
|
Made an attempt at read address. So superficially that leaves only the force interrupts.
|
2017-01-01 20:55:09 -05:00 |
|
Thomas Harte
|
f94f34f053
|
Made an attempt at read track. Which means process_input_bit can't just swallow syncs any more; it now reports them as tokens of type ::Sync.
|
2017-01-01 20:39:19 -05:00 |
|
Thomas Harte
|
c994fa39f6
|
Ensured spin-up doesn't occur if there's no motor line.
|
2016-12-31 16:18:30 -05:00 |
|
Thomas Harte
|
1ea4f0d79d
|
Made an attempt to implement 'write track' and ensure that 'write sector' can't end without announcing that it has ended writing.
|
2016-12-31 16:01:44 -05:00 |
|
Thomas Harte
|
8eb21c6702
|
The "MFM...Byte"s aren't MFM-specific, they're relevant to both FM and MFM encoding. So renamed them. Also slimmed syntax within MFM.cpp mostly where emigration from the Acorn disk analyser had left a residue of lengthy namespace specification.
|
2016-12-31 15:25:11 -05:00 |
|
Thomas Harte
|
a8bc9d830e
|
Removed leftover very temporary debugging aid.
|
2016-12-28 23:03:05 -05:00 |
|
Thomas Harte
|
e4000bd060
|
Added some even more verbose logging; slightly simplified write loop logic, and decided it's definitely write_byte that's responsible for CRC generator feeding.
|
2016-12-28 21:24:19 -05:00 |
|
Thomas Harte
|
4adcb46665
|
Fixed FM-mode CRC generation.
|
2016-12-28 19:51:27 -05:00 |
|
Thomas Harte
|
1277a67f9a
|
Introduced data_mode_ to replace is_reading_data_, representing that there are now three possible modes. When writing, any input from the read head won't affect the CRC generator.
|
2016-12-28 19:26:21 -05:00 |
|
Thomas Harte
|
7a627b782d
|
Reintroduced writing of MFM sync marks when writing a sector.
|
2016-12-28 18:48:50 -05:00 |
|
Thomas Harte
|
a568172758
|
Made steps towards proper CRC generation. Am currently comparing against Oric disk images, as — amongst other things — they include precomputed CRCs.
|
2016-12-28 18:29:37 -05:00 |
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Thomas Harte
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9c0f622a2e
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Started working CRC checking into the 1770. Discovered immediately that my generated CRC does not match that built into the Oric disk images. So mine is pretty-much certainly wrong. An opportunity for learning!
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2016-12-26 16:46:26 -05:00 |
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Thomas Harte
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0490a47058
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Worked on the all-around framework for decoding sectors back from tracks when closing down a file. Hit the wall that the parser is more observant of CRCs than the WD. No, really. So I guess I have to stop avoiding that whole issue.
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2016-12-26 14:24:33 -05:00 |
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Thomas Harte
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83c433c142
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Deviated from the data sheet, which seems likely to be correct. Hence removed a whole load of the temporary logging.
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2016-12-26 12:48:49 -05:00 |
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Thomas Harte
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742c5df367
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With lots of logging arising temporarily, fixed bug whereby conversion to a patched track would lead to holding a track with a distinct measure of time, leading to improperly-placed patches.
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2016-12-25 22:00:39 -05:00 |
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Thomas Harte
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acc35885cd
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Attempted to reduce track invalidations.
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2016-12-25 20:38:25 -05:00 |
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Thomas Harte
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c0a1264ab0
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Slightly improved legibility.
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2016-12-25 20:19:47 -05:00 |
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Thomas Harte
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e2b829f68e
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Made an attempt to write the proper address mark.
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2016-12-25 20:15:07 -05:00 |
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Thomas Harte
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beaa868079
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Factored the MFM parser out into encodings.
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2016-12-25 20:00:57 -05:00 |
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Thomas Harte
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74e98fd097
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Made an attempt to write actual data (albeit that CRC calculation is still missing).
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2016-12-25 19:18:45 -05:00 |
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Thomas Harte
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98be6ede45
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Shuffled a little to reduce risk of overflow, ensured writing is a loop, still seem to be writing too quickly for some reason.
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2016-12-25 16:13:05 -05:00 |
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Thomas Harte
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d2ad2c756e
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Added enough shovelling to write rubbish for an entire sector.
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2016-12-25 15:46:49 -05:00 |
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Thomas Harte
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aceb7e3b6b
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Started implementing write sector on the 1770, immediately deciding it would be useful to have a callback for end-of-queued-data-written from disk controller. So had a go at implementing that, naively. More investigation required.
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2016-12-25 12:31:38 -05:00 |
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Thomas Harte
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901f19f89c
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Added enough stuff that SSDs attached to a 1770 will now reach the entry point for writing.
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2016-12-25 09:46:12 -05:00 |
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Thomas Harte
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c304db0f5a
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Deintegrated the busy flag and the interrupt request line, as the latter is reset by status reads. Which also means I can start reporting the WD INTRQ line status directly from the Microdisc. That appears to be correct, rather than honouring the Microdisc IRQ select there.
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2016-12-06 21:16:29 -05:00 |
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Thomas Harte
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ca50606e1d
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Restored Vic audio.
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2016-12-03 17:10:47 -05:00 |
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Thomas Harte
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36bc558798
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Converted all 'Components' to postfix underscores.
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2016-12-03 10:51:09 -05:00 |
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Thomas Harte
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81ee834530
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As well as a bunch of logging, reinstated rotation position preservation across tracks.
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2016-12-02 18:36:47 -05:00 |
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Thomas Harte
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93c573bfa9
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Implemented missing status bits (other than the index hole), and a head loading delay for the Microdisc.
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2016-12-01 21:13:16 -05:00 |
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Thomas Harte
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0a0775c3bd
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Removed earlier hacky solution.
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2016-12-01 20:16:11 -05:00 |
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Thomas Harte
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442986ee2c
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Introduced a head loading path for 1793 machines.
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2016-12-01 20:12:22 -05:00 |
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Thomas Harte
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82899f2f47
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Ensured flag setting is atomic, removed duplication of interrupt request versus busy, found better names for the personality testers, unified delegate protocol.
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2016-12-01 07:41:52 -05:00 |
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Thomas Harte
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b31fd11470
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Fixed reporting of data request line, initial status values.
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2016-11-30 22:39:55 -05:00 |
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Thomas Harte
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2222cb65d6
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Split the status up into flags, assembled into a register upon demand. Attempted to implement some of the differences between the 1770/1772 and 1773/1793. Albeit with a motor fix still in place.
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2016-11-30 22:26:02 -05:00 |
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Thomas Harte
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84cb07613d
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Checked some documentation more thoroughly; the 1793 has quite different spin-up (/head load) semantics. So it's another distinct personality. Grrr.
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2016-11-27 20:39:08 -08:00 |
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Thomas Harte
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02ba1f220f
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The '72 seems to be a '70 with altered timing. So worth differentiating.
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2016-11-27 21:06:17 +08:00 |
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Thomas Harte
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2c01f9dbed
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Added meaningful TODOs.
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2016-11-27 08:42:39 +08:00 |
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Thomas Harte
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2f459690d4
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It would appear the 1770 and 1773 actually differ in relation to the (non-sensical) ability not to spin-up for a Type 2, and whether a side compare can occur. So the WD1770 class now requires a personality to be specified. Which it singly fails to honour.
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2016-11-26 23:29:30 +08:00 |
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Thomas Harte
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d8ecc52de8
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Temporarily disabled spin-down as harmful to the status register if following anything other than a Type 1 command.
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2016-11-26 22:27:20 +08:00 |
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