Thomas Harte
cfb75b58ca
Pulls all 6502 MicroOp sequences into the main operations_ table.
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This will make state restoration somewhat more tractable.
2020-03-29 18:36:41 -04:00
Thomas Harte
4fbe983527
Provisionally adds State and get_state to the 6502.
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`set_state` may be a little more complicated, requiring a way to advance in single-cycle steps **without applying bus accesses**.
2020-03-28 00:33:27 -04:00
Thomas Harte
a51fe70498
Standardises cast syntax.
2020-03-06 21:55:00 -05:00
Thomas Harte
b971e2a42c
Adds get_is_resetting to the Z80, eliminating the CPC's custom version.
2020-02-29 19:58:25 -05:00
Thomas Harte
01faffd5bf
Corrects memptr behaviour of OTIR/OTDR and INIR/INDR.
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This seemingly perfects memptr.
2020-02-27 20:55:43 -05:00
Thomas Harte
26de5be07c
Corrects memptr behaviour of LDIR/LDDR and CPIR/CPDR.
2020-02-27 20:44:53 -05:00
Thomas Harte
87474d5916
Corrects memptr behaviour of OUT (C), 0.
2020-02-27 20:38:27 -05:00
Thomas Harte
06163165d9
Corrects memptr effect of LD rr, (nn).
2020-02-26 22:22:54 -05:00
Thomas Harte
ec82c075be
Fixes memptr for IN C, (C).
2020-02-26 22:19:37 -05:00
Thomas Harte
3b0df172a7
Corrects memptr behaviour of JP nn.
2020-02-26 22:02:15 -05:00
Thomas Harte
7058dbc3cc
Corrects memptr for LD HL, (nn).
2020-02-26 21:54:49 -05:00
Thomas Harte
b64de89d2d
Corrects JR memptrs.
2020-02-26 21:47:34 -05:00
Thomas Harte
8878396339
Corrects DJNZ memptr behaviour.
2020-02-26 21:42:31 -05:00
Thomas Harte
3097c4ccae
Improves MEMPTR testing and some results.
2020-02-24 23:32:18 -05:00
Thomas Harte
7959d243f6
Adds single-stepping. Of a kind.
2020-02-24 23:31:42 -05:00
Thomas Harte
79dd402bc8
Consolidates different test port input selection.
2020-02-23 16:12:28 -05:00
Thomas Harte
3f3229851b
Implements MEMPTR for IN.
2020-02-23 00:32:33 -05:00
Thomas Harte
dca79ea10e
Requires trace flag currently set.
2020-01-18 22:52:53 -05:00
Thomas Harte
b7fd4de32f
Ensures a one-instruction latency on the trace flag.
2020-01-18 22:06:00 -05:00
Thomas Harte
9f2f547932
Adds and satisfies test on the function code word.
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Thanks to ijor's "68000 Address and Bus Error Stack Frame" re: contents.
2020-01-04 23:58:07 -05:00
Thomas Harte
f0d5bbecf2
Introduces a test of stack contents after an address error.
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Fixes: stacked PC, address of fault.
2020-01-04 23:22:07 -05:00
Thomas Harte
a28c52c250
Fixes A7-relative JSRs.
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I completely withdraw my earlier statement re: the test cases.
2020-01-04 22:22:33 -05:00
Thomas Harte
7de1181213
Make a new guess at post-overflow DIV flags, based on tests.
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Specifically: for DIVU, stick with the current guess of a fixed set. For DIVS, leave N and Z alone.
2020-01-03 23:44:49 -05:00
Thomas Harte
c7a5b054db
There's no TODO here; overflow is always 0 for a 16x16 multiply.
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... and the original 68000 doesn't support 32x32 multiplies.
2020-01-03 22:44:19 -05:00
Thomas Harte
2f8078db22
Switches to should_log as a global when I'm hacking about.
2020-01-02 20:15:48 -05:00
Thomas Harte
5be30b1f7b
Introduces further comparative tests, prompting a new CHK fix.
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Specifically: how to set N when both is_under and is_over are true, and to eliminate a failure fully to prefetch in the longer addressing modes.
2020-01-01 19:11:36 -05:00
Thomas Harte
b184426f2b
Ensure that an interrupt from a STOP doesn't return to the STOP.
2020-01-01 14:51:47 -05:00
Thomas Harte
1de4f179c0
Adds more thorough comment on the bus program used.
2019-12-25 19:49:49 -05:00
Thomas Harte
3cb5684d95
Fixes RTR: the whole top half of the SR should be preserved.
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Specifically, the 68000 Reference Manual says: "The supervisor portion of the status register is unaffected." Clearly when I first read that I misread it as the supervisor _flag_ (rather than _portion_) should be preserved.
2019-12-25 19:49:20 -05:00
Thomas Harte
274867579b
Deploys constexpr as a stricter const.
2019-12-22 00:22:17 -05:00
Thomas Harte
cf16f41939
Makes value8_high/low and value16 branchless.
2019-12-21 20:58:37 -05:00
Thomas Harte
08f2877382
I think the 68000 actually loads a byte value onto both the upper and lower data lines.
2019-12-21 20:37:03 -05:00
Thomas Harte
a3e64cae41
Corrects SBCD carry.
2019-12-17 22:16:02 -05:00
Thomas Harte
8a2ac87209
Reverted SBCD/NBCD V behaviour.
2019-12-16 23:08:59 -05:00
Thomas Harte
096b447b4b
Corrects MOVE -(An), SR/CCR, which was not previously decrementing.
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Also adds a safety check against other instances of the same error. There seem to be none.
2019-12-16 22:38:54 -05:00
Thomas Harte
84167af54f
Corrects CHK N flag.
2019-12-16 20:01:33 -05:00
Thomas Harte
8be26502c4
Fixes NBCD -(An)+, adds some additional comments.
2019-12-16 20:01:19 -05:00
Thomas Harte
4c068e9bb8
Corrects flags on CMPA.w.
2019-12-15 20:39:47 -05:00
Thomas Harte
dc1abd874e
Corrects indentation typo.
2019-12-14 23:52:53 -05:00
Thomas Harte
4dd235f677
Adds supervisor/user to logged flags in trace mode.
2019-12-08 22:39:10 -05:00
Thomas Harte
407cc78c78
Extends to offer simpler 8-bit access handling.
2019-12-08 20:19:44 -05:00
Thomas Harte
b12136691a
Corrects comment.
2019-11-18 23:46:33 -05:00
Thomas Harte
db03b03276
Corrects [AND/OR/EOR].bw Dn, -(An) to decrement destination.
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It was previously doing a predecrement on the internal source address, which is unused. This fixes at least Dan Dare III and Silkworm.
2019-11-09 11:25:23 -05:00
Thomas Harte
6afefa107e
Resolves unused variable warning.
2019-11-05 23:18:25 -05:00
Thomas Harte
07582cee4a
BusGrant is a further signal I will need.
2019-11-03 21:10:42 -05:00
Thomas Harte
a67e0014a4
Fixes video base address and mono/colour monitor value.
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Now I see a GEM desktop. In blue.
2019-11-02 19:36:15 -04:00
Thomas Harte
c070f2100c
Attempts to regularise data bus access.
2019-11-01 23:01:06 -04:00
Thomas Harte
1c154131f9
Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.
2019-10-29 22:36:29 -04:00
Thomas Harte
ecc0cea5a1
Added a potential branch for the newer TOS memory map.
2019-10-26 16:52:06 -04:00
Thomas Harte
8a14f5d814
Updates to Xcode11 recommended project settings.
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The updated compiler also flagged a potential issue with CPU::Z80::Register not being a namespace re: 'Refresh' versus CPU::Z80::PartialMachineCycle. I don't entirely see it, but this fixes the problem.
I also finally figured out what the compiler was trying to tell me about ROMRequester.xib.
2019-09-22 12:13:56 -04:00
