6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-07 19:05:38 +00:00
Code Issues Projects Releases Wiki Activity
10,650 Commits 8 Branches 121 Tags 496 MiB
29169ffed7
Commit Graph

37 Commits

Author SHA1 Message Date
Thomas Harte
bb84a5a474 Enable various ADB-controller interrupts. 2023-08-21 15:35:13 -04:00
Thomas Harte
8578dfbf22 Eliminate various other errant spaces. 2023-05-16 16:40:09 -04:00
Thomas Harte
2b56b7be0d Simplify namespace syntax. 2023-05-10 16:02:18 -05:00
Thomas Harte
5d1970d201 Adds a hacky different guess at how register access might work. 2021-02-19 21:46:18 -05:00
Thomas Harte
2e9065b34c Increases number of fixed initial values. 2021-02-18 22:48:53 -05:00
Thomas Harte
eccf5ca043 Makes first effort to wire up the ADB vertical blank input. 
However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.
 2021-02-14 22:20:58 -05:00
Thomas Harte
82312d3b59 Provide a more convincing version of port output. 2021-02-08 18:14:08 -05:00
Thomas Harte
77b1efd176 Sets sensible 'reset' values. 2021-02-07 21:53:57 -05:00
Thomas Harte
acfab1dfb3 Starts to make some effort at timers. 2021-02-06 21:02:44 -05:00
Thomas Harte
5eddc92846 Implements direction registers. 2021-01-28 21:06:11 -05:00
Thomas Harte
c8beb59172 Attempts properly to track ADB bus activity. 
Output is not yet a valid ADB stream. Work to do.
 2021-01-25 17:43:22 -05:00
Thomas Harte
8789ffda15 Corrects performer storage, RMW/W confusion, implicit casts, port readback. 2021-01-24 22:30:42 -05:00
Thomas Harte
e8e604dc3c Attempts to wire up M50470 and GLU. 
Resulting in an unexpected interest in R15. Bugs to find, I guess.
 2021-01-24 18:07:05 -05:00
Thomas Harte
57e0fdfadc Ensures ADB microcontroller is clocked. 
And runs at the 'correct' speed (i.e. modulo my instruction-by-instruction implementation).
 2021-01-23 22:55:12 -05:00
Thomas Harte
adef2e9b4e Starts formalising end conditions. 2021-01-21 22:36:44 -05:00
Thomas Harte
0fafbf5092 Completes M50740 instruction set. 2021-01-21 19:08:38 -05:00
Thomas Harte
df1bc18fb3 Pushes ahead to what will be my first interaction with the T flag. 2021-01-20 20:27:09 -05:00
Thomas Harte
9f12ce2fb8 Corrects RTS, adds the remainder of the direct flag manipulations. 2021-01-20 20:16:55 -05:00
Thomas Harte
b9672c0669 Gets beyond a prima facie convincing JSR/RET. 2021-01-20 18:21:44 -05:00
Thomas Harte
e58608b25a Gets as far as executing a first loop. 2021-01-20 18:15:24 -05:00
Thomas Harte
e502d76371 Corrects immediate instruction length, muddles through to having to parse a second program segment. 
Albeit with JSR not yet properly implemented.
 2021-01-19 22:12:18 -05:00
Thomas Harte
b0c790f3c6 Adds enough flags seemingly to reach an ASL. 2021-01-19 21:54:15 -05:00
Thomas Harte
aa478cd222 Stops trying to force bit ID into the addressing mode. 2021-01-19 21:51:01 -05:00
Thomas Harte
c78c121159 Succeeds at executing a single instruction. 2021-01-18 20:16:01 -05:00
Thomas Harte
e71e506883 This assert is redundant; not worth an extra #include. 2021-01-18 17:56:40 -05:00
Thomas Harte
a601ac0cab Corrects performer population, lookup, calls. 2021-01-18 17:53:14 -05:00
Thomas Harte
ec0018df79 Routes in the ADB keyboard ROM. This should get as far as parsing. 2021-01-18 16:59:49 -05:00
Thomas Harte
8b19c523cf Starts to bend towards getting some performers in motion. 2021-01-18 16:45:52 -05:00
Thomas Harte
5ace61f9b9 Continues walking very slowly towards cached execution. 2021-01-18 11:20:45 -05:00
Thomas Harte
ad03858c6e Switches performers to member functions. Very slightly starts work on M50740 performers. 2021-01-17 20:53:11 -05:00
Thomas Harte
54b26c7991 Bends to using 8-bit lookups for M50740 instructions. 2021-01-17 20:03:36 -05:00
Thomas Harte
17c3a3eb4b Seeks to switch to maintaining a bank of performers. 
My thinking here is that for really simple processors there'll be 256 or less, meaning that they can be stored by simple uint8_t; for every other processor I can currently think of it'll likely be uint16_t.

Either way, that's a much better outcome than using plain pointers, which on architectures I currently build for will always be 8 bytes. For the simple processors I can get eight times as much into the cache; for the others four times.
 2021-01-17 19:38:23 -05:00
Thomas Harte
5f413a38df Switches all American-style dates. 
I'd failed to configure my new computer appropriately, it seems.
 2021-01-16 22:09:19 -05:00
Thomas Harte
8860d0ff51 Starts to establish the CachingExecutor. 2021-01-16 22:06:16 -05:00
Thomas Harte
8bd471fa3c Corrects recursive call. 2021-01-16 21:50:48 -05:00
Thomas Harte
cd6ac51aa6 Muddles along to generating functions. 
Albeit right now without a body.
 2021-01-16 21:45:44 -05:00
Thomas Harte
10caa1a1fb Steps gingerly towards execution. 2021-01-16 20:51:02 -05:00