407 Commits

Author	SHA1	Message	Date
Thomas Harte	2935848f35	Adopted header/header/data/data pattern. But still not complete joy.	2016-08-17 08:03:34 -04:00
Thomas Harte	dfe9fb83ef	This proves that bytes are being deposited properly. For the first 36 anyway, and with no announcement.	2016-08-16 21:09:50 -04:00
Thomas Harte	12f8aff65b	Lengths I'd taken seem to have been for dipoles, not single poles. So I just doubled the clock rate. Also I was producing each dipole as high then low, when they should probably be low then high. The Vic now at least recognises that something is happening on the tape.	2016-08-16 19:46:53 -04:00
Thomas Harte	ca2dc6b6c4	Ensured ROMs survive in the new memory model.	2016-08-15 19:56:01 -04:00
Thomas Harte	38aec44d85	Made sufficient changes for the Vic itself to believe it can recast a PRG as a tape and insert it that way. So now the ball is in the court of: how the heck are Commodore tapes encoded?	2016-08-15 19:44:41 -04:00
Thomas Harte	547aefb696	Slightly adjusted PRG strategy, made a note about where next.	2016-08-14 16:36:42 -04:00
Thomas Harte	d9016909ed	Added some wiring for PAL/NTSC mode switching on the Vic, making an attempt to simplify the whole loop of having different clock rates.	2016-08-14 13:33:20 -04:00
Thomas Harte	a547b7e1d8	Took basic steps towards supporting memory expansions.	2016-08-13 17:21:25 -04:00
Thomas Harte	142774be37	Collapsed 6560 template to a more direct loop, albeit with quite a bit still left to fix.	2016-08-09 21:10:53 -04:00
Thomas Harte	12bad8f23f	Turned the 6560 into an ordinary template, similar to the rest of the project, albeit right now with a fairly shonky internal implementation. Fixed a Mac-specific interface sizing issue.	2016-08-09 20:41:05 -04:00
Thomas Harte	285a288c80	Switched to two cycles of options loading, meaning that they get set before files are inserted. Might need some further work?	2016-08-07 21:48:09 -04:00
Thomas Harte	be54d8040e	Made a first stab at having automatic loading be optional. But things are currently arranged such that the machine options are communicated too late to have an effect. So work to do.	2016-08-06 17:39:27 -04:00
Thomas Harte	3e65450a54	Converted the 6560 fully into a template; worked on allowing the typer to run at a much faster rate where hardware has some trigger by which it can request the next key.	2016-08-06 14:33:24 -04:00
Thomas Harte	d832e5e10d	Reduced 1540 PLL to running at 4Mhz. Which is possibly correct (?) Made minor change to avoid divide if possible.	2016-08-02 21:28:50 -04:00
Thomas Harte	5d40d70c92	Fixed 6560 addressing error, added an autotyper for Vic disks (more work potentially needed), fixed semantics for testing whether a 6502 is about to reset.	2016-08-01 10:32:32 -04:00
Thomas Harte	bc10b3ee9a	It appears the problem is as simple as sectors being counted from zero.	2016-08-01 10:08:38 -04:00
Thomas Harte	f5e4ea3351	Some minor tidying, lots more of the caveman stuff as I try to determine what I'm doing wrong.	2016-08-01 09:43:08 -04:00
Thomas Harte	18744cd98b	Slightly updated comments, switched to 1540 ROM so as very slightly to improve loading time.	2016-08-01 04:37:30 -04:00
Thomas Harte	b43a7381ae	Fixed framing and first-byte-after-sync signalling. Hacked together as parts of it are, loading now appears to work!	2016-08-01 04:25:11 -04:00
Thomas Harte	41893b5ef6	Put in the absolute minimum logic for drive motor emulation. Drive appears to be attempting head steps.	2016-07-31 19:38:51 -04:00
Thomas Harte	740ea0b7e2	Added overflow-flag setting logic and ensured disk ROM gets through regardless of ROM/disk installation order.	2016-07-31 19:33:18 -04:00
Thomas Harte	0945049cd3	Made attempt to connect sync detect and then apply appropriate windowing, posting bytes to the appropriate place.	2016-07-31 18:29:44 -04:00
Thomas Harte	198fbbedc7	Reeled back all appropriate pieces of caveman debugging.	2016-07-31 13:42:34 -04:00
Thomas Harte	2332f72875	Formalised clock-rate multiplication within disk drives, discovered that the stepper didn't have ideal behaviour for my timed event loop and hence nailed down the semantics a ilttle more. ... (obiter: the 1540 now appears to discern the correct sequence of bits. Framing is off in my test printfs but that's neither here nor there).	2016-07-31 13:32:30 -04:00
Thomas Harte	8f62211f5e	Wired up the 1540 as a PLL delegate. Which prima facie means it should start receiving a bit stream. Except that I clearly have something in the timing way off — either my flux transitions are far too short or I need to significantly increase the clock rate on the PLL.	2016-07-29 12:08:18 -04:00
Thomas Harte	89a1881fef	Started turning the 1540 into an actual disk drive.	2016-07-29 11:03:09 -04:00
Thomas Harte	ada2f073e0	Completed handing of the disk all the way to the 1540.	2016-07-10 16:24:46 -04:00
Thomas Harte	6cfc514c2d	Made the rote changes necessary to attempt to open and to supply a G64 to the Vic.	2016-07-10 12:57:17 -04:00
Thomas Harte	4ca6883f7c	Disabled attachment of a 1540 again, as I probably need to move to opening an actual disk image next.	2016-07-10 08:03:36 -04:00
Thomas Harte	824d9ea92b	Added further comments.	2016-07-10 08:01:16 -04:00
Thomas Harte	d8334edf4a	Started trying to clean up, including commuting the C1540 source file name to match its class name but mainly by adding documentation.	2016-07-10 07:46:20 -04:00
Thomas Harte	c0ab45a73d	Disabled a bunch of the caveman debug logging.	2016-07-09 22:29:11 -04:00
Thomas Harte	f589d639db	Okay, so it seems that sync also works the other way around.	2016-07-09 22:25:44 -04:00
Thomas Harte	693c8b2438	After all that, it seems likely that inputs just aren't inverted for the Vic.	2016-07-09 20:03:38 -04:00
Thomas Harte	656cd211d7	Was transmitting bit levels backwards (probably?); 1540 now acknowledges byte received.	2016-07-09 18:06:49 -04:00
Thomas Harte	7cc4bf3fe7	Hit and hope is getting me nowhere. Time to unit test this thing.	2016-07-09 15:40:25 -04:00
Thomas Harte	8827597363	Messier and messier, but I've at least attempted to implement hardware attention acknowledge.	2016-07-08 19:00:39 -04:00
Thomas Harte	9a08ef61cb	Still fumbling in the margins: made an effort not to imply that the 1540 is forever reading syncs.	2016-07-07 22:13:18 -04:00
Thomas Harte	199c0e27e0	Mostly just random guesses now, to be honest. It's approaching the end of my window for the morning.	2016-07-07 07:16:36 -04:00
Thomas Harte	81e6cc34e5	Per the ROM disassembly, the Vic's VIA outputs are inverted for the benefit of the serial bus.	2016-07-07 06:57:21 -04:00
Thomas Harte	c9479f923b	The inversion of truth was clearly just a problematic API. Got explicit. LineLevel might need to become more pervasive.	2016-07-07 06:44:13 -04:00
Thomas Harte	dcb86a027a	Okay, so the 1540 doesn't toggle the actual attention line. I don't know what it does yet but this helps.	2016-07-06 22:31:14 -04:00
Thomas Harte	1baf21827c	Since the ROM is well disassembled, let's actually try to be a 1541 first.	2016-07-06 22:17:32 -04:00
Thomas Harte	4f174786b5	Fixed potential buffer overrun.	2016-07-06 21:39:09 -04:00
Thomas Harte	f64cd8cfcb	Quick fixes properly to declare the DriveVIA, to ensure its interrupts take effect, and to wire ATN IN to CA1 rather than CB2.	2016-07-06 20:22:46 -04:00
Thomas Harte	428fcdb978	Centralised and improved serial logging.	2016-07-06 07:46:21 -04:00
Thomas Harte	8819711bc8	Threw in the second VIA as a currently clearly incorrect thing.	2016-07-05 22:22:09 -04:00
Thomas Harte	93c2bb80a2	Improved a comment, added independent C[A/B]2 input mode.	2016-07-05 21:11:51 -04:00
Thomas Harte	6c4fa4ec5d	Improved commenting and initial state communication.	2016-07-05 20:57:31 -04:00
Thomas Harte	1e6d90de17	Made an attempt properly to deal with initial bus state.	2016-07-05 20:52:33 -04:00