6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-04 15:05:36 +00:00
Code Issues Projects Releases Wiki Activity
8,402 Commits 8 Branches 121 Tags 496 MiB
29e5ecc282
Commit Graph

661 Commits

Author SHA1 Message Date
Thomas Harte
2c1f2edcf2 Introduce failing 'clock' test case. 
i.e. a few seconds of the Workbench 1.0 clock application.
 2021-10-31 16:12:51 -07:00
Thomas Harte
9e6ffaad7d Introduce test case for fill mode. 2021-10-31 14:12:26 -07:00
Thomas Harte
edb75e69cb Implement bitplane modulos. 2021-10-29 11:29:22 -07:00
Thomas Harte
5ebc59dd1f Introduce additional test cases. 2021-10-26 20:58:38 -07:00
Thomas Harte
4d7ce3792f Use additional test cases. 2021-10-25 21:48:43 -07:00
Thomas Harte
dc8701a929 Introduce some additional Blitter test cases. 2021-10-25 21:40:20 -07:00
Thomas Harte
15ed4a0d09 Introduce failing test case for sector decoding. 2021-10-16 10:48:32 -07:00
Thomas Harte
aa6b0f07b7 Correct filename. 2021-10-16 05:37:46 -07:00
Thomas Harte
6b0dd19442 Name file appropriately: the logo comes from Kickstart. 2021-10-09 08:02:15 -07:00
Thomas Harte
da286d5ae8 Switch spaces to tabs. 2021-10-04 05:27:25 -07:00
Thomas Harte
ad90c6b6ce Now that this is getting close, don't stop at the first error. 2021-09-29 22:19:34 -04:00
Thomas Harte
0c998d60cb Correct test logic for line draws that repeatedly write to the same address. 2021-09-28 21:45:55 -04:00
Thomas Harte
1dfc36f311 Flip loop, add modulo mappings. 2021-09-26 18:15:32 -04:00
Thomas Harte
1c03ff1d37 Fix bltdptl to bltbptl misstatement; remove pre-DMA writes. 2021-09-26 18:14:50 -04:00
Thomas Harte
19dd2f92bd Implements test case. Failing at present, naturally. 2021-09-25 21:52:41 -04:00
Thomas Harte
acfaa016a0 Adds a capture of traffic leading up to the Workbench boot logo. 
Around which to construct a test case.
 2021-09-25 18:10:07 -04:00
Thomas Harte
fa800bb809 Introduces code for minterm application. 2021-09-20 19:13:23 -04:00
Thomas Harte
e402e690b0 Assume and test that divide-by-zero posts the PC of the offending instruction. 2021-08-07 17:51:00 -04:00
Thomas Harte
b4ec9d70da Adds the CNT input. 2021-08-03 22:19:41 -04:00
Thomas Harte
738999a8b7 Further expands list of applied tests. 2021-08-03 22:08:50 -04:00
Thomas Harte
34c1cc5693 Adds entry points for all remaining tests. 
Failing now: the TB123s, which are TOD related, both CIA2 tests, and CIA1TAB (which I think needs me to implement Port B output toggling).
 2021-08-03 17:19:35 -04:00
Thomas Harte
f0ef45f0ca Introduces two further tests. 2021-08-03 16:58:51 -04:00
Thomas Harte
f576baf214 I'm not yet sure this is the best approach, but starts trying to make use of Lorenz's 6526 tests. 2021-07-30 21:21:16 -04:00
Thomas Harte
94907b51aa Remove redundant parameter. 2021-07-06 20:47:49 -04:00
Thomas Harte
0085265d13 Test for a longer period; fix expected tone 1 count. 2021-07-06 20:46:22 -04:00
Thomas Harte
8e0893bd42 Clarifies control flow. 2021-07-06 20:28:32 -04:00
Thomas Harte
704dc9bdcb Improves test, to assert that state toggles happen at interrupts. 2021-07-06 20:25:32 -04:00
Thomas Harte
3e6b804896 Switches to linked 1/50/1000 Hz timers, and per-interrupt state toggling. 2021-07-06 20:12:44 -04:00
Thomas Harte
f371221dba Add a quick test of tone generator 1. 2021-07-02 23:57:11 -04:00
Thomas Harte
27b0579ec6 Avoid stack-error test case. 
Also test that the interrupt is generated on the downward stroke.
 2021-07-02 23:55:43 -04:00
Thomas Harte
283092cfbc With a unit test in aid, corrects some lingering TimedInterruptSource issues. 2021-07-02 23:41:19 -04:00
Thomas Harte
fbf1adef05 Introduces unit test and thereby seemingly fixes get_next_sequence_point. 
There's still improper output in the actual machine though, so maybe something else is afoot?
 2021-06-18 17:44:17 -04:00
Thomas Harte
f27e331462 Updates autotests to new RomFetcher world. 2021-06-06 20:34:55 -04:00
Thomas Harte
37dcf61130 Add timing tests, fix +3 discrepancy. 2021-04-23 22:29:57 -04:00
Thomas Harte
a1511f9600 Establishes that the 48/128kb contention patterns can be derived from my partial machine cycles alone. 2021-04-14 20:15:40 -04:00
Thomas Harte
68a04f4e6a Adds IN/OUT I/D [R] to complete tests. 2021-04-13 22:00:24 -04:00
Thomas Harte
0d61902b10 Adds CP[I/D/IR/DR] tests. 2021-04-13 20:03:11 -04:00
Thomas Harte
3eec210b30 Adds LDI/LDD/LDIR/LDDR tests. 2021-04-13 20:00:29 -04:00
Thomas Harte
2e70b5eb9f Advances to EX (SP), HL, leaving only [LD/CP/IN/OT][I/D]{R}. 2021-04-13 19:45:29 -04:00
Thomas Harte
8a3bfb8672 Adds an IN/OUT test. 2021-04-13 17:55:51 -04:00
Thomas Harte
06f1e64177 Advances to IO. 2021-04-12 21:41:20 -04:00
Thomas Harte
b42780173a Establishes that there really is no Read4 and Read4Pre distinction. 
Will finish these unit tests, then clean up.
 2021-04-12 20:54:10 -04:00
Thomas Harte
36c8821c4c Reaches the halfway point in tests. 2021-04-12 17:29:03 -04:00
Thomas Harte
9347fe5f44 Advances to next failing test: LD (ii+n), n. 2021-04-12 17:11:58 -04:00
Thomas Harte
e82367def3 Switches to test-conformant behaviour for (IX/IY+n) opcode fetches. 2021-04-11 23:01:00 -04:00
Thomas Harte
47c5a243aa Restructures, the better to explore errors. 2021-04-10 21:32:42 -04:00
Thomas Harte
070e359d82 Introduces failing test for BIT b, (ii+n). 2021-04-10 18:00:23 -04:00
Thomas Harte
400f54e508 Introduces failing test for bit b, (hl). 2021-04-10 12:04:48 -04:00
Thomas Harte
e0736435f8 Makes assumption that the address bus just holds its value during an internal operation. 2021-04-10 12:00:53 -04:00
Thomas Harte
b09c5538c6 Adds failing test for simple (ii+n) tests. 2021-04-09 21:28:35 -04:00