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Commit Graph

10021 Commits

Author SHA1 Message Date
Thomas Harte
17bbe27c9a As an experiment, performed some very basic moving of playfield composition outside of the pixel loop. 2015-08-13 21:32:22 +01:00
Thomas Harte
033655835a My understanding now is that object position counting will begin the cycle after the call is made, not that cycle, and that the timer loops just once, with the logic for counter pumping being whether the relevant flag is still set, irregardless of whether the counter is still going. 2015-08-13 18:59:23 +01:00
Thomas Harte
b440fed323 Fixed a couple of incorrect references to horizontal constants or calculations where the intention is to use vertical. 2015-08-13 18:29:07 +01:00
Thomas Harte
323aa27e13 Fixed: paging is based directly on the access, independent of the read/write line (since it isn't actually exposed to catridges). 2015-08-13 15:04:30 +01:00
Thomas Harte
59c872ada6 Attempted to reintroduce suitably noted emergency flyback. To re-enable auto-selection of PAL. 2015-08-13 14:55:53 +01:00
Thomas Harte
9838e01cc1 Made a first attempt at paging. 2015-08-13 13:24:02 +01:00
Thomas Harte
9ca57b80a7 Minor steps to help with diagnostics; all commented out or merely to benefit with breakpoint placement. 2015-08-13 08:43:10 +01:00
Thomas Harte
cc98534f94 Added test for NOP, discovering the undocumented ones to be the incorrect length. 2015-08-13 07:32:50 +01:00
Thomas Harte
6616265d93 Fixed collision tests, added a few more timing tests. 2015-08-13 03:33:45 +01:00
Thomas Harte
dd0f17130a Found and fixed some timing errors in absolute indexed and in (indirect), y addressing modes: neither is able in write or read-modify-write modes to shave a cycle as then can when reading. 2015-08-13 02:58:39 +01:00
Thomas Harte
975836c30f Added a quick snippet test, discovering that I've cut a cycle from read/modify/writes. 2015-08-13 02:18:41 +01:00
Thomas Harte
503d684af0 Added a couple of timing tests, both of which seem to pass for now. 2015-08-13 01:55:23 +01:00
Thomas Harte
e8f70398c1 Added one basic timing test, for now: implied nop should be two cycles. 2015-08-13 01:06:56 +01:00
Thomas Harte
d19f8ed507 Removed the implicit reset upon 6502 startup, adding a reset line. Hence all tests now pass again. Added an empty shell for timing tests, the all-RAM 6502 now counting bus cycles. 2015-08-13 00:51:06 +01:00
Thomas Harte
687816d470 Made some attempted simplifications, implemented collisions. 2015-08-13 00:31:57 +01:00
Thomas Harte
aebf636528 Ensured the PIA timer resumes its normal tick rate after being read; fixed those spaces that had crept in where tabs should be. 2015-08-10 16:55:16 +01:00
Thomas Harte
42677f5f83 Fixed association of motion registers and actual registers. 2015-08-10 16:43:45 +01:00
Thomas Harte
0e52b7365e Removed redundant code. 2015-08-10 16:42:25 +01:00
Thomas Harte
2dde2efff0 Attempted to standardise object counters. 2015-08-10 15:09:40 +01:00
Thomas Harte
a228969655 This should happen every fourth cycle. 2015-08-10 08:16:17 +01:00
Thomas Harte
3c27306a8e My counter was going the wrong way. 2015-08-10 00:33:37 +01:00
Thomas Harte
a4e52cc4db Made an attempt to switch to a hardware-accurate object timer model. Without yet perfect success. 2015-08-10 00:20:18 +01:00
Thomas Harte
cd67e31e64 Made a first attempt at switching a little closer to TIA's real internal counter setup. 2015-08-09 22:47:11 +01:00
Thomas Harte
987be65a59 Made a quick attempt at reimplementing skip-to-the-end logic for ready waits. 2015-08-09 02:42:01 -04:00
Thomas Harte
eb23a493e5 Switched back to one texel per colour clock, at least for now. Attempted to break _RGBA assumption within the cathode ray view. 2015-08-05 23:36:04 -04:00
Thomas Harte
fd36f13baf The cathode ray view no longer hard codes the frame size. So that's one less coupling. Doubled pixel output size to give sufficient sampling detail to capture the NTSC colour clock (ummm, hopefully). 2015-08-05 21:45:47 -04:00
Thomas Harte
67e82c713f Broke assumption that every item in a vertex description is a short, specifically turning lateral into a byte. Which buys me a byte for phase, if that's sufficient. 2015-08-05 21:12:33 -04:00
Thomas Harte
5644b3a1cc Fixed scanline sizing and fill issues, as well as shortening vsync to the correct Atari length. 2015-08-05 20:55:27 -04:00
Thomas Harte
265d1d5b24 Merge branch 'EdgeTriggeredVSync' 2015-08-05 20:30:02 -04:00
Thomas Harte
84d1c2e47d Fixed end of sync time calculation and ensured the pretend capacitor is emptied by the decision to retrace and doesn't refill during retrace. 2015-08-05 20:29:20 -04:00
Thomas Harte
04c2640b15 Made a quick attempt to allow vsync triggers only on the raising edge of a sync signal. Will need to investigate more thoroughly. 2015-08-03 08:42:05 -04:00
Thomas Harte
5313b48ebd I'm ashamed to admit, I: played with numbers until enough things looked stable such that I can investigate other things. Discovery: my PAL autodetection was way off. Fixed, hopefully. 2015-08-02 20:32:18 -04:00
Thomas Harte
55017b78a5 Made an attempt to unify my variable storage (and, technically, to get beam size correct across the frame). 2015-08-02 19:30:45 -04:00
Thomas Harte
6e52e5df1c Full separate 'lateral' usage is go. Also probably at some point I need to throw in a phase property, which this new flexibility will help with. 2015-08-02 14:32:29 -04:00
Thomas Harte
3ab6585789 Started making the format of data included in a CRTFrame less a matter of variously hard-coded magic constants. Which will allow me to separate the idea of an internal lateral position from the direct texture coordinate, avoiding precision sampling errors at the top and bottom. 2015-08-02 14:25:21 -04:00
Thomas Harte
be421587ad Eliminated the vertical retrace counter; vertical retrace ends when the beam gets back to the top. 2015-08-02 13:48:35 -04:00
Thomas Harte
de4f2bf5dd Maybe the 10 lines resource I saw meant 10 lines including charge time? 2015-07-31 19:00:40 -04:00
Thomas Harte
5f1d76e855 Can't seem to find any documentation: assumed horizontal sync is generated during vertical. 2015-07-31 18:49:02 -04:00
Thomas Harte
c1a12ad4df Fix to make sure end of vertical sync is always correctly spotted as an event, rather than just happening off the books. So I can now watch Joust roll to its heart's content. 2015-07-31 18:15:59 -04:00
Thomas Harte
9c91f1a2eb Added an attempt at NTSC/PAL autodetection, based on number of missed vertical syncs. 2015-07-31 18:04:33 -04:00
Thomas Harte
a5d66e9dd6 Factored out a few more constants, started trying to ensure there's enough slack and the mechanisms in place for the CathodeRayView to hold onto two frames if it desires, for potential phosphor simulation, switched once again to additive blending — much more like a real CRT — and added a sine function across the width of spans per my understanding of how an electron gun actually fires.
Why do all this when overall timing is still so far off? It helps me more easily see how overall timing is so far off.
2015-07-31 17:47:10 -04:00
Thomas Harte
c1d1fb65cb Made an attempt properly to emulate the RDY line and the Atari's use of it. 2015-07-31 16:54:20 -04:00
Thomas Harte
53dd5c8f16 Trying to fix my RDY line emulation. Switched to PAL timings, at least temporarily, since it's starting to make a difference. 2015-07-31 16:44:53 -04:00
Thomas Harte
e4615cda2e Switched back to unrealistic solid raster beams for the time being. 2015-07-30 23:01:59 -04:00
Thomas Harte
39bfbf1000 Attempted ball graphics enable delay. 2015-07-30 23:01:28 -04:00
Thomas Harte
6ad3fbbaf2 Slowed flywheel adjustments a little, the better to highlight phase errors for the time being. 2015-07-30 23:00:54 -04:00
Thomas Harte
78e66d2577 Added an attempt at ball rendering. 2015-07-30 21:30:00 -04:00
Thomas Harte
cfe758daa0 A tweak here, a tweak there, to help with debugging. 2015-07-30 21:29:40 -04:00
Thomas Harte
a95b36a53d Made first attempt at missile display. In Enduro, at least, one seems to work but the other seems to be absent. 2015-07-30 21:09:18 -04:00
Thomas Harte
1b7846f09b Made a first attempt at the sprite latches. Hopefully this should make a few more Activision logos, etc, show up correctly. 2015-07-30 20:52:26 -04:00