1404 Commits

Author	SHA1	Message	Date
Thomas Harte	b30fda3c36	Localise shorthand Storage; note that labels may be unused.	2025-10-29 12:19:25 -04:00
Thomas Harte	7e43b40415	Merge pull request #1617 from TomHarte/NoWarnings ... Resolve x86-related build warnings plus various whitespace deficiencies.	2025-10-29 12:16:53 -04:00
Thomas Harte	c5dc65fc61	Resolve various whitespace errors.	2025-10-29 11:50:56 -04:00
Thomas Harte	5e789b4b0c	Grab last PC operation address; ensure power-on reset is predictable.	2025-10-29 09:03:35 -04:00
Thomas Harte	9ff09a45be	Allow is-1mhz decision to observe shortened addresses.	2025-10-28 21:32:09 -04:00
Thomas Harte	fc02a3d34b	Merge branch 'master' into BBCNew6502	2025-10-28 21:22:30 -04:00
Thomas Harte	dd25d387fe	Allow for __COUNTER__ potentially not starting at 0.	2025-10-28 21:07:03 -04:00
Thomas Harte	80a503f317	Adjust formatting.	2025-10-28 20:54:05 -04:00
Thomas Harte	5aa9168dd6	Make overflow private.	2025-10-28 20:49:59 -04:00
Thomas Harte	b3f01fe314	Move carry into private storage.	2025-10-28 20:43:57 -04:00
Thomas Harte	e688d87c22	Move negative and zero into private storage.	2025-10-28 18:23:16 -04:00
Thomas Harte	332fb2f384	Make decimal flag private.	2025-10-28 17:34:31 -04:00
Thomas Harte	5332bcd6b4	Clarify set/get difference; make interrupt flag storage private.	2025-10-28 17:32:10 -04:00
Thomas Harte	55c59e6164	Start hiding Flags implementation.	2025-10-28 17:24:53 -04:00
Thomas Harte	80bfa1859f	Merge branch 'Turbo6502' into BBCNew6502	2025-10-27 22:22:11 -04:00
Thomas Harte	58e1880773	Eliminate 'addr' side effects.	2025-10-27 22:14:48 -04:00
Thomas Harte	c8c4c99f09	Incorporate IRQ timing test; accept that it must be tested within the access macro.	2025-10-27 21:32:52 -04:00
Thomas Harte	350f424055	Merge branch 'Turbo6502' into BBCNew6502	2025-10-27 17:27:04 -04:00
Thomas Harte	bc5b7a6725	Unpublish WriteableReader.	2025-10-27 17:01:29 -04:00
Thomas Harte	7b4e71e6dd	Just use the preprocessor then. Yuck.	2025-10-27 13:10:24 -04:00
Thomas Harte	a32202ab72	Be more overt in trying to avoid "use of undeclared identifier".	2025-10-27 12:52:57 -04:00
Thomas Harte	193c027c8b	To simplify debugging, add non-constructing path. ... This won't have any effect on generated code.	2025-10-27 12:42:00 -04:00
Thomas Harte	3dd07b6ac1	To simplify debugging, add non-constructing path. ... This won't have any effect on generated code.	2025-10-27 12:41:17 -04:00
Thomas Harte	12d912b627	Add insurance against bus handler not writing.	2025-10-27 12:37:38 -04:00
Thomas Harte	f847a72696	Add insurance against bus handler not writing.	2025-10-27 12:37:14 -04:00
Thomas Harte	967c3f6dba	Ensure NMI isn't perpetual.	2025-10-26 21:56:35 -04:00
Thomas Harte	cbc6477431	Ensure NMI isn't perpetual.	2025-10-26 21:55:09 -04:00
Thomas Harte	cba96aee37	Honour interrupt flag.	2025-10-25 17:02:48 -04:00
Thomas Harte	17325834b5	Implement is_resetting.	2025-10-25 17:02:27 -04:00
Thomas Harte	4df49d9f18	Round out interrupt signalling.	2025-10-25 08:54:25 -04:00
Thomas Harte	8b04608d68	Implement STP and WAI.	2025-10-24 23:47:30 -04:00
Thomas Harte	2bac276870	Populate type_of.	2025-10-24 23:42:40 -04:00
Thomas Harte	213f9850e7	Add WDC65C02 decoder.	2025-10-24 23:41:55 -04:00
Thomas Harte	378bffbf84	Implement BBR/BBS.	2025-10-24 23:37:18 -04:00
Thomas Harte	c291d5313d	Fix PLX.	2025-10-24 22:22:05 -04:00
Thomas Harte	e81233c586	Implement JMP (abs,x).	2025-10-24 22:16:36 -04:00
Thomas Harte	b946029394	Correct 65c02 JMPAbsoluteIndirect.	2025-10-24 21:57:53 -04:00
Thomas Harte	fe79a1231d	Add extra cycle to immediate decimal arithmetic.	2025-10-24 21:39:14 -04:00
Thomas Harte	76a5872d17	Install extra cycle for 65c02 decimal arithmetic.	2025-10-24 21:24:05 -04:00
Thomas Harte	0d72c75e15	Give modify stalls to fast NOPs.	2025-10-24 16:51:07 -04:00
Thomas Harte	2e0e89c494	Implement fast modify path; fix more NOPs.	2025-10-24 16:43:57 -04:00
Thomas Harte	7d6b7a5874	Adjust 0x?b NOPs.	2025-10-24 15:57:54 -04:00
Thomas Harte	48f8ddf53a	65c02: make AbsoluteIndexed modify cycle harmless.	2025-10-24 15:55:45 -04:00
Thomas Harte	9aae07b737	Implement zero indirect addressing mode.	2025-10-24 15:53:55 -04:00
Thomas Harte	d7abdc8017	Transfer ownership of final PC increment, to accomodate 65c02 misreads.	2025-10-24 15:49:17 -04:00
Thomas Harte	cb81156835	65c02: distinguish 'fast' NOPs from regular.	2025-10-24 13:52:32 -04:00
Thomas Harte	1fd8d94e2e	Import further NOPs.	2025-10-24 13:33:10 -04:00
Thomas Harte	e4fe127444	Fix 65c02 modify cycles: read/read/write, not read/write/write.	2025-10-24 13:30:10 -04:00
Thomas Harte	aeabd5f113	Patch in TSB and TRB.	2025-10-24 12:33:13 -04:00
Thomas Harte	58f7d4065c	65c02: support single-cycle NOP.	2025-10-24 12:29:53 -04:00