Thomas Harte
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ee71be0e7e
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Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
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2017-08-21 21:56:42 -04:00 |
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Thomas Harte
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42b5b66305
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Remove the 6502's use of runtime polymorphism in favour of ordinary templating.
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2017-08-16 11:56:52 -04:00 |
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Thomas Harte
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4abd62e62b
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Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
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2017-07-27 22:05:29 -04:00 |
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Thomas Harte
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279c369a1f
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Switched to Cycles as the result from the 6502 perform_bus_operation, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.
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2017-07-25 22:21:09 -04:00 |
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Thomas Harte
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9435c1e12a
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The 1540 is now a ClockReceiver.
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2017-07-24 22:32:41 -04:00 |
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Thomas Harte
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efdac2ce8c
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The 6522 is now a ClockReceiver.
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2017-07-24 22:29:09 -04:00 |
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Thomas Harte
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8a2bdb8d22
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Converted the TimedEventLoop and the things that sit atop it into ClockReceivers.
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2017-07-24 21:19:05 -04:00 |
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Thomas Harte
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83628b285b
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Experimentally turned the 6502 into a clock receiver. No problem encountered.
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2017-07-22 21:52:21 -04:00 |
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Thomas Harte
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f931cd582d
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Switched to use of std::vector in those few remaining places where I was still using a unique_ptr to a native type and newing for myself. So, some of my earliest bits of code.
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2017-07-16 13:54:07 -04:00 |
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Thomas Harte
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0808e9b6fb
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Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.
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2017-05-14 22:08:15 -04:00 |
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Thomas Harte
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e01f3f06c8
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Completed curly bracket movement.
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2017-03-26 14:34:47 -04:00 |
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Thomas Harte
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063a62372f
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The Commodore serial bus and C1540 are now postfix underscorers.
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2016-12-03 13:14:03 -05:00 |
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Thomas Harte
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4fab794747
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Added a direct-to-two-cycles emulation path for 6522 owners.
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2016-10-27 21:13:25 -04:00 |
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Thomas Harte
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6292ac5b26
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Yet more .hpp clean(s)ing.
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2016-10-20 21:15:21 -04:00 |
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Thomas Harte
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572d5587d9
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Made a first stab at enabling multi-disk machines and thereby obeying (some of) the Plus 3's status register.
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2016-09-25 21:24:16 -04:00 |
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Thomas Harte
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9bbcbd1001
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Renamed class, intending to turn a Disk::Drive into literally just that, and have a thing with a PLL that consumes events be a Controller.
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2016-09-25 20:05:56 -04:00 |
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Thomas Harte
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56c0d70c1f
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Gave disks their own namespace.
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2016-08-27 17:15:09 -04:00 |
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Thomas Harte
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d832e5e10d
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Reduced 1540 PLL to running at 4Mhz. Which is possibly correct (?) Made minor change to avoid divide if possible.
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2016-08-02 21:28:50 -04:00 |
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Thomas Harte
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bc10b3ee9a
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It appears the problem is as simple as sectors being counted from zero.
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2016-08-01 10:08:38 -04:00 |
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Thomas Harte
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f5e4ea3351
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Some minor tidying, lots more of the caveman stuff as I try to determine what I'm doing wrong.
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2016-08-01 09:43:08 -04:00 |
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Thomas Harte
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18744cd98b
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Slightly updated comments, switched to 1540 ROM so as very slightly to improve loading time.
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2016-08-01 04:37:30 -04:00 |
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Thomas Harte
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b43a7381ae
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Fixed framing and first-byte-after-sync signalling. Hacked together as parts of it are, loading now appears to work!
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2016-08-01 04:25:11 -04:00 |
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Thomas Harte
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41893b5ef6
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Put in the absolute minimum logic for drive motor emulation. Drive appears to be attempting head steps.
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2016-07-31 19:38:51 -04:00 |
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Thomas Harte
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740ea0b7e2
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Added overflow-flag setting logic and ensured disk ROM gets through regardless of ROM/disk installation order.
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2016-07-31 19:33:18 -04:00 |
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Thomas Harte
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0945049cd3
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Made attempt to connect sync detect and then apply appropriate windowing, posting bytes to the appropriate place.
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2016-07-31 18:29:44 -04:00 |
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Thomas Harte
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198fbbedc7
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Reeled back all appropriate pieces of caveman debugging.
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2016-07-31 13:42:34 -04:00 |
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Thomas Harte
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2332f72875
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Formalised clock-rate multiplication within disk drives, discovered that the stepper didn't have ideal behaviour for my timed event loop and hence nailed down the semantics a ilttle more.
(obiter: the 1540 now appears to discern the correct sequence of bits. Framing is off in my test printfs but that's neither here nor there).
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2016-07-31 13:32:30 -04:00 |
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Thomas Harte
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8f62211f5e
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Wired up the 1540 as a PLL delegate. Which prima facie means it should start receiving a bit stream. Except that I clearly have something in the timing way off — either my flux transitions are far too short or I need to significantly increase the clock rate on the PLL.
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2016-07-29 12:08:18 -04:00 |
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Thomas Harte
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89a1881fef
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Started turning the 1540 into an actual disk drive.
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2016-07-29 11:03:09 -04:00 |
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Thomas Harte
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ada2f073e0
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Completed handing of the disk all the way to the 1540.
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2016-07-10 16:24:46 -04:00 |
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Thomas Harte
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824d9ea92b
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Added further comments.
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2016-07-10 08:01:16 -04:00 |
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Thomas Harte
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d8334edf4a
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Started trying to clean up, including commuting the C1540 source file name to match its class name but mainly by adding documentation.
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2016-07-10 07:46:20 -04:00 |
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Thomas Harte
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c0ab45a73d
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Disabled a bunch of the caveman debug logging.
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2016-07-09 22:29:11 -04:00 |
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Thomas Harte
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f589d639db
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Okay, so it seems that sync also works the other way around.
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2016-07-09 22:25:44 -04:00 |
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Thomas Harte
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693c8b2438
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After all that, it seems likely that inputs just aren't inverted for the Vic.
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2016-07-09 20:03:38 -04:00 |
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Thomas Harte
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656cd211d7
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Was transmitting bit levels backwards (probably?); 1540 now acknowledges byte received.
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2016-07-09 18:06:49 -04:00 |
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Thomas Harte
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7cc4bf3fe7
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Hit and hope is getting me nowhere. Time to unit test this thing.
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2016-07-09 15:40:25 -04:00 |
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Thomas Harte
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8827597363
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Messier and messier, but I've at least attempted to implement hardware attention acknowledge.
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2016-07-08 19:00:39 -04:00 |
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Thomas Harte
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9a08ef61cb
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Still fumbling in the margins: made an effort not to imply that the 1540 is forever reading syncs.
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2016-07-07 22:13:18 -04:00 |
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Thomas Harte
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199c0e27e0
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Mostly just random guesses now, to be honest. It's approaching the end of my window for the morning.
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2016-07-07 07:16:36 -04:00 |
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Thomas Harte
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c9479f923b
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The inversion of truth was clearly just a problematic API. Got explicit. LineLevel might need to become more pervasive.
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2016-07-07 06:44:13 -04:00 |
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Thomas Harte
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dcb86a027a
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Okay, so the 1540 doesn't toggle the actual attention line. I don't know what it does yet but this helps.
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2016-07-06 22:31:14 -04:00 |
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Thomas Harte
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1baf21827c
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Since the ROM is well disassembled, let's actually try to be a 1541 first.
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2016-07-06 22:17:32 -04:00 |
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Thomas Harte
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f64cd8cfcb
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Quick fixes properly to declare the DriveVIA, to ensure its interrupts take effect, and to wire ATN IN to CA1 rather than CB2.
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2016-07-06 20:22:46 -04:00 |
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Thomas Harte
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428fcdb978
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Centralised and improved serial logging.
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2016-07-06 07:46:21 -04:00 |
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Thomas Harte
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8819711bc8
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Threw in the second VIA as a currently clearly incorrect thing.
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2016-07-05 22:22:09 -04:00 |
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Thomas Harte
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93c2bb80a2
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Improved a comment, added independent C[A/B]2 input mode.
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2016-07-05 21:11:51 -04:00 |
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Thomas Harte
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6c4fa4ec5d
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Improved commenting and initial state communication.
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2016-07-05 20:57:31 -04:00 |
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Thomas Harte
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1e6d90de17
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Made an attempt properly to deal with initial bus state.
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2016-07-05 20:52:33 -04:00 |
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Thomas Harte
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c3b7d24293
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It appears that the attention line is also wired to CB2. So the ball is back in the 6522's court.
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2016-07-05 19:19:46 -04:00 |
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