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Author SHA1 Message Date
Thomas Harte
5c68b6cc21 Fixed display enable reset when there's no adjustment area. A practical lesson in failure to factor. 2017-07-31 22:16:08 -04:00
Thomas Harte
ffaa627820 Fixed frame restart when there is no adjustment period. 2017-07-31 22:13:45 -04:00
Thomas Harte
f742fd5d4a Made basic attempt to get something on screen: white where the display is enabled, black for the border. 2017-07-31 22:13:20 -04:00
Thomas Harte
69b99fe127 Transferred ownership of the CRT to the CRTC bus handler, to give it easy access. 2017-07-31 22:04:52 -04:00
Thomas Harte
5a396f6787 Added an explicit cast. 2017-07-31 22:04:31 -04:00
Thomas Harte
cb0dc7b434 I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing. 2017-07-31 22:01:54 -04:00
Thomas Harte
e28829bd1b Corrected CRTC timing, gave it someone to talk to and a means with which to talk. 2017-07-31 20:14:46 -04:00
Thomas Harte
68ceeab610 Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation. 2017-07-31 19:56:59 -04:00
Thomas Harte
68dca9d047 Made a first attempt at ROM paging, with pretty much the same scheme that'll be needed for 128kb support. 2017-07-31 19:37:28 -04:00
Thomas Harte
d88ca151f4 Added a first attempt at output port decoding. Just logging for now. 2017-07-31 19:25:10 -04:00
Thomas Harte
3c90218c3d With a very basic stab at something a bit like the memory map (sans paging), execution begins. 2017-07-31 19:15:43 -04:00
Thomas Harte
afd409c883 Ensured that ROM images are loaded and passed to the Amstrad CPC. 2017-07-31 18:44:49 -04:00
Thomas Harte
26b6c03a2a Re-enabled the address sanitiser as a development tool. 2017-07-31 07:30:07 -04:00
Thomas Harte
9c04d851e4 Added the basics necessary to get the CPU ticking over, at a nominal 4Mhz but with the wait states that I currently believe to be accurate. 2017-07-31 07:29:50 -04:00
Thomas Harte
1d6fe11906 Added an instance of Outputs::CRT::CRT. So progress is now: select CDT, up comes a blank window. 2017-07-31 07:16:51 -04:00
Thomas Harte
c0f1313830 Performed sufficient wiring to get to the point where attempting to load a CDT creates an instance of the Amstrad CPC and then fails only because the thing vends a nullptr CRT. 2017-07-30 22:05:29 -04:00
Thomas Harte
fb51fadf00 Merge branch 'master' into CPC 2017-07-30 21:29:31 -04:00
Thomas Harte
55fd9122d0 Slightly relaxed vertical sync testing. 2017-07-30 21:19:42 -04:00
Thomas Harte
5b5720fac0 Added to the static analyser the most basic through-path for Amstrad CPC content. 2017-07-30 21:15:20 -04:00
Thomas Harte
d25d7d7d40 Added the Amstrad CPC as a named target and declared support for its CDT file format. 2017-07-29 21:56:33 -04:00
Thomas Harte
ba4f2d8917 Merge branch 'master' into VerticalSync 2017-07-29 21:45:22 -04:00
Thomas Harte
a2aec39633 Merge pull request #167 from TomHarte/VerticalSync 
Adjusts vertical sync detection
 2017-07-29 21:44:47 -04:00
Thomas Harte
0bf4fdc9af Simplified slightly. 2017-07-29 21:37:59 -04:00
Thomas Harte
ed8c73eb14 Ensured lengthy constant sync can't appear to be two sync pulses, regardless of other interruption. 2017-07-29 18:25:04 -04:00
Thomas Harte
3528a7f78b Made an attempt at triggering vertical sync the expected number of time after it begins, regardless of total length. 2017-07-29 17:33:52 -04:00
Thomas Harte
54bcc40192 With an eye towards being more accurate as to vertical sync recognition: acknowledged that the detection period varies between PAL and NTSC. 2017-07-29 14:53:53 -04:00
Thomas Harte
4b5e9ffb83 Ensured is_at_end_ is initially cleared by default. 2017-07-27 22:22:43 -04:00
Thomas Harte
a7f5f035a6 Merge pull request #166 from TomHarte/NoRefs 
Standardises on `const [Half]Cycles`
 2017-07-27 22:07:05 -04:00
Thomas Harte
4abd62e62b Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty. 2017-07-27 22:05:29 -04:00
Thomas Harte
1fb158b297 Merge pull request #165 from TomHarte/HalfCycleTyper 
Brings `Typer` into the new `run_for` orthodoxy
 2017-07-27 21:56:02 -04:00
Thomas Harte
968d2bb8ba Brought Typer into the new run_for orthodoxy, making it easier to clock consistently regardless of unit. Which necessitated adding a negative operator for WrappedInts. 2017-07-27 21:53:45 -04:00
Thomas Harte
92a3dfe44a Merge pull request #164 from TomHarte/NoInt 
Revokes the operator bool() on WrappedInt and simplifies/generalises HalfClockReceiver
 2017-07-27 21:41:04 -04:00
Thomas Harte
9ef232157b Revoked the operator bool() on WrappedInt as providing an indirect means for implicit but incorrect assignment to unwrapped ints. Got explicit about run_for intention and simplified HalfClockReceiver slightly by building a lossy and a flushing conversion to Cycles into HalfCycles. Adapted the all-RAM Z80 properly to return HalfCycles. 2017-07-27 21:38:50 -04:00
Thomas Harte
b9f4f7a530 Merge pull request #163 from TomHarte/WaitSampling 
Adjusts the timing of the Z80's wait line sampling to be on a half clock and better regularises 'action' partial bus cycles
 2017-07-27 21:19:29 -04:00
Thomas Harte
761afad118 Corrected timestamp return, and its testing by the 6502 timing tests. 2017-07-27 21:19:16 -04:00
Thomas Harte
8848ebbd4f Formalised set_interrupt_line's optional parameter as being a count of HalfCycles; corrected PartialMachineCycle.is_wait and effected the proper timing for counter reset on a ZX81. 2017-07-27 21:10:14 -04:00
Thomas Harte
37950143fc Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests. 2017-07-27 20:17:13 -04:00
Thomas Harte
25fd95044c Merge pull request #154 from TomHarte/Memptr 
Introduces a subset of necessary test cases for the Z80 memptr register, and corrects implementation to match
 2017-07-27 08:10:22 -04:00
Thomas Harte
1da24d10fd Corrected a couple of build errors. 2017-07-27 08:05:14 -04:00
Thomas Harte
60e374dca3 Merge branch 'master' into Memptr 2017-07-27 07:54:25 -04:00
Thomas Harte
7a65f91575 Merge pull request #162 from TomHarte/ClockReceiverHolder 
Completes revocation of ClockReceiver
 2017-07-27 07:43:12 -04:00
Thomas Harte
6f8b558724 Revoked dead #include. 2017-07-27 07:41:59 -04:00
Thomas Harte
1a88b62bf7 Merge branch 'master' into ClockReceiverHolder 2017-07-27 07:41:20 -04:00
Thomas Harte
8361756dc4 Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock. 2017-07-27 07:40:02 -04:00
Thomas Harte
273299028e Merge pull request #161 from TomHarte/Z80WaitSampling 
Doubles the timing precision used by the Z80 up to HalfCycles
 2017-07-27 07:39:36 -04:00
Thomas Harte
847e49ccdf Corrected timestamp reporting by the all-RAM Z80. 2017-07-26 19:47:39 -04:00
Thomas Harte
81a3899381 Adjusted the Z80 formally to communicate in terms of half cycles rather than whole. 2017-07-26 19:42:00 -04:00
Thomas Harte
9257a3f6d7 Added test for 16-bit arithmetic, and fixed implementation. 2017-07-26 19:04:52 -04:00
Thomas Harte
728143247d Added a test for RLD and RRD. Which already passes. 2017-07-26 18:56:35 -04:00
Thomas Harte
6ec4e4e3d7 Merge branch 'master' into Memptr 2017-07-25 23:01:34 -04:00