70 Commits

Author	SHA1	Message	Date
Thomas Harte	4ac4da908c	Reduce TODOs, do _something_ with border colour.	2024-03-21 21:40:11 -04:00
Thomas Harte	66e62857c4	Give ostensibly clean timing to the CRT.	2024-03-21 21:29:53 -04:00
Thomas Harte	bbc0d8b050	Count time in phase correctly.	2024-03-21 21:15:25 -04:00
Thomas Harte	0f8bc416d1	Make first, faulty step into displaying a field.	2024-03-21 21:10:55 -04:00
Thomas Harte	2ec235170e	Finish the thought on magic constants.	2024-03-21 20:45:17 -04:00
Thomas Harte	2de1a2dd0d	Install and properly clock a CRT.	2024-03-21 20:41:24 -04:00
Thomas Harte	1f49c3b113	Give sound and video somewhere to read from.	2024-03-21 20:22:20 -04:00
Thomas Harte	5c645fb3c2	Switch to a fixed output clock; retain addresses.	2024-03-21 11:51:29 -04:00
Thomas Harte	40b5227f0b	Deliver all addresses to the video outputter.	2024-03-21 11:24:47 -04:00
Thomas Harte	847dba8f07	Divide input pixel rate.	2024-03-21 11:03:28 -04:00
Thomas Harte	417c6c4629	Announce changes.	2024-03-21 10:51:52 -04:00
Thomas Harte	2d6a4d490e	Add dummy retrace interrupt.	2024-03-21 10:02:56 -04:00
Thomas Harte	a6ec870872	Capture more audio detail.	2024-03-21 09:47:53 -04:00
Thomas Harte	389541be6d	Pipe further sound parameters; obey divider.	2024-03-20 14:43:47 -04:00
Thomas Harte	208f3e24de	Audio ticks are now included.	2024-03-20 14:30:21 -04:00
Thomas Harte	1341816791	Break apart, switching to delegates for interrupts.	2024-03-20 14:26:56 -04:00
Thomas Harte	08673ff021	Switch to macro blocks of execution; flail around audio.	2024-03-20 11:42:37 -04:00
Thomas Harte	3a2d9c6082	Give user access to ROM; clean up a touch.	2024-03-19 20:26:17 -04:00
Thomas Harte	43a3959b8f	Don't data abort on missing low ROM.	2024-03-19 15:06:01 -04:00
Thomas Harte	85a738acff	Get rigorous on exception addresses.	2024-03-19 15:03:31 -04:00
Thomas Harte	2ad6bb099b	Begin foray into disassembly.	2024-03-19 11:34:10 -04:00
Thomas Harte	9d858bc61b	IRQ and FIQ should also store PC+4.	2024-03-18 14:08:08 -04:00
Thomas Harte	612c9ce49a	Transfer logging responsibility.	2024-03-18 11:09:29 -04:00
Thomas Harte	7b1f800387	Extend I2C state machine.	2024-03-17 21:55:19 -04:00
Thomas Harte	47e9279bd4	Add a target for I2C activity.	2024-03-16 15:00:23 -04:00
Thomas Harte	635efd0212	Clear keyboard interrupts.	2024-03-15 23:19:26 -04:00
Thomas Harte	1c1d2891c7	Adjust IRQ/FIQ return addresses.	2024-03-15 21:59:38 -04:00
Thomas Harte	1979d2e5ba	Don't set interrupt flags before capture.	2024-03-15 21:34:39 -04:00
Thomas Harte	3a899ea4be	Add test coverage for STM descending, proving nothing.	2024-03-15 14:55:17 -04:00
Thomas Harte	9d08282e28	Add enough of a keyboard to respond to reset.	2024-03-15 10:57:18 -04:00
Thomas Harte	18154278d1	Add minor note on where next.	2024-03-14 21:54:20 -04:00
Thomas Harte	bc27e3998d	Fix downward block data transfers.	2024-03-14 21:09:51 -04:00
Thomas Harte	19fa0b8945	Shush logging, momentarily.	2024-03-14 10:53:38 -04:00
Thomas Harte	4987bdfec9	Throw less.	2024-03-14 10:43:51 -04:00
Thomas Harte	0e4615564d	Make bit masks easily testable; expand logging.	2024-03-13 14:31:26 -04:00
Thomas Harte	7aeea535a1	Reduce branchiness.	2024-03-13 11:02:52 -04:00
Thomas Harte	2ed031e440	Prepare for additional devices.	2024-03-12 21:23:22 -04:00
Thomas Harte	c6b91559e1	Attempt to wire up timer interrupts.	2024-03-12 11:34:31 -04:00
Thomas Harte	6efc41ded7	Come to conclusion on R15; fix link values.	2024-03-12 10:42:09 -04:00
Thomas Harte	8b3c0abe93	Take another swing at R15 as a destination.	2024-03-12 09:13:05 -04:00
Thomas Harte	a5ebac1b29	Add RISC OS 3.11 to catalogue, while bug hunting.	2024-03-11 22:19:14 -04:00
Thomas Harte	1ccfae885c	Remove extra slashes.	2024-03-11 15:06:17 -04:00
Thomas Harte	e7457461ba	Reduce magic constants.	2024-03-11 14:49:03 -04:00
Thomas Harte	a28c97c0de	Simplify privilege test.	2024-03-11 12:14:00 -04:00
Thomas Harte	21278d028c	Correct unaligned accesses.	2024-03-10 21:56:19 -04:00
Thomas Harte	fbc273f114	Add invented model for tests.	2024-03-10 21:45:56 -04:00
Thomas Harte	47f7340dfc	Start hacking in some ARM tests.	2024-03-08 22:54:42 -05:00
Thomas Harte	fdef8901ab	Double down on uint32_t.	2024-03-08 14:13:34 -05:00
Thomas Harte	a46ec4cffb	Up clock rate to 24Mhz.	2024-03-07 22:16:58 -05:00
Thomas Harte	9bb5dc3c2b	Fix inclusive range.	2024-03-07 19:40:34 -05:00