Thomas Harte
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2203499215
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Enables -Wreorder and corrects a few of the more trivial fixes thereby suggested.
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2017-11-09 22:14:22 -05:00 |
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Thomas Harte
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ad9df4bb90
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Commutes uint8_t *, uint16_t *, uint32_t *, size_t, off_t and long to functional-style casts.
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2017-10-21 22:30:15 -04:00 |
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Thomas Harte
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5e3e91373a
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Switches all unsigned int and double casts to functional style.
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2017-10-21 19:49:04 -04:00 |
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Thomas Harte
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4abd62e62b
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Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
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2017-07-27 22:05:29 -04:00 |
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Thomas Harte
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b82bef95f3
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Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
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2017-07-24 20:10:05 -04:00 |
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Thomas Harte
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c2a7dffa7d
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Converted the ZX80/81 video component into a ClockReceiver. As it happens, it's most convenient to take the half-cycle bus here.
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2017-07-22 23:02:28 -04:00 |
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Thomas Harte
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ed28260aaf
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Hardens the ZX80/81 video routines to ensure they never try to push data into the future and don't double-count time when pixels would ostensibly run into sync. You could previously see the CRT being handed negative run lengths if sync interrupted pixels or if a run of more than 320 pixels (my arbitrary buffer size) occurred, with corresponding poor behaviour given my use of unsigned numbers.
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2017-07-09 19:33:05 -04:00 |
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Thomas Harte
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30e93979d2
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Removed data work if sync is enabled; in that case no data is output.
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2017-07-08 21:01:07 -04:00 |
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Thomas Harte
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b9dbb6bcf8
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Discovered my timing error: the I/R <-> A loads should take an extra cycle. This means the ZX80 now finally takes the correct 207 cycles per line. Fixed the video output wave to be clocked at the appropriate rate.
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2017-06-12 18:55:04 -04:00 |
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Thomas Harte
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ba5f34f827
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Narrowed view to the centre 80% of a frame.
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2017-06-11 17:24:32 -04:00 |
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Thomas Harte
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d910a4fd38
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Adjusted to signal an interrupt during the refresh cycle rather than weirdly just afterwards. Which cuts video timing down by 4 cycles a line. There still might be a problem here somewhere though, as I'm getting 206 cycles/line and the internet states it should be 207.
Also: lots of printfs have grown temporarily as I try to figure out what I'm doing so wrong as to break loading.
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2017-06-11 13:32:20 -04:00 |
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Thomas Harte
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e3ee9604a5
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Added comments.
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2017-06-06 18:01:33 -04:00 |
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Thomas Harte
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8c66e1d99d
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Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data.
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2017-06-06 17:53:23 -04:00 |
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