Thomas Harte
b037c76da6
Add public interface for everything except HALT and BUS REQ/etc.
...
... neither of which are used by machines I currently implement.
2022-05-23 20:55:01 -04:00
Thomas Harte
9cac4ca317
Add MOVE to/from USP.
2022-05-23 20:42:41 -04:00
Thomas Harte
34e5f39571
Ensure that running exactly up to a boundary gives the bus handler the next microcycle to contemplate.
2022-05-23 15:11:33 -04:00
Thomas Harte
e0a279344c
Codify the existence of special cases, implement NOP and RESET.
2022-05-23 15:09:46 -04:00
Thomas Harte
e2f4db3e45
Shuffle more of the flow controller methods into their proper place.
2022-05-23 12:06:14 -04:00
Thomas Harte
c1837af84a
Add notes to self on work remaining.
2022-05-23 11:02:31 -04:00
Thomas Harte
a87f6a28c9
Fix LINK A7.
2022-05-23 10:43:17 -04:00
Thomas Harte
98325325b1
Fix UNLINK A7.
2022-05-23 10:27:44 -04:00
Thomas Harte
26bf66e3f8
Fix shifts and rolls.
2022-05-23 10:09:46 -04:00
Thomas Harte
363cd97154
Resolve double definition of did_shift.
2022-05-23 10:07:24 -04:00
Thomas Harte
c6b3281274
Attempt the shifts and rolls.
2022-05-23 09:29:19 -04:00
Thomas Harte
1e8adc2bd9
Fix MOVEP to R.
2022-05-23 09:00:37 -04:00
Thomas Harte
c73021cf3c
Implement MOVE.
2022-05-23 08:46:06 -04:00
Thomas Harte
1b3acf9cd8
Eliminate assumption.
2022-05-23 08:18:37 -04:00
Thomas Harte
c8ede400eb
Fix RTE.
2022-05-22 21:17:28 -04:00
Thomas Harte
269263eecf
Implement RTE, RTS, RTR.
2022-05-22 21:16:38 -04:00
Thomas Harte
faef5633f8
Ensure MOVE from SR has an effective address to write to.
2022-05-22 20:52:00 -04:00
Thomas Harte
7d1f1a3175
Implement MOVE [to/from] [CCR/SR].
2022-05-22 19:45:22 -04:00
Thomas Harte
4e34727195
Fully implement TAS.
2022-05-22 16:14:03 -04:00
Thomas Harte
1dd6ed6ae3
Implement TAS Dn, with detour for other TASes.
2022-05-22 16:08:30 -04:00
Thomas Harte
3b68b9a83b
Implement PEA.
2022-05-22 11:27:38 -04:00
Thomas Harte
4279ce87ea
Implement LEA.
2022-05-22 08:29:12 -04:00
Thomas Harte
3c1c4f89e9
Add MULU/S functionality, though not timing.
2022-05-22 08:02:32 -04:00
Thomas Harte
4a6512f5d5
Reduce dispatch boilerplate.
2022-05-22 07:39:16 -04:00
Thomas Harte
284f23c6ea
Implement JMP.
2022-05-22 07:16:38 -04:00
Thomas Harte
11a9a5c126
Use common macros for the two forms of Perform.
2022-05-22 07:08:14 -04:00
Thomas Harte
4993801741
Add missing prefetch to BSET, BCHG, BCLR.
2022-05-21 21:05:05 -04:00
Thomas Harte
4b35899a12
Bcc: properly establish offset.
2022-05-21 20:59:34 -04:00
Thomas Harte
1304e930eb
DBcc is two-operand.
2022-05-21 20:06:03 -04:00
Thomas Harte
94288d5a94
Excludes DBcc from standard operand fetch.
2022-05-21 19:53:28 -04:00
Thomas Harte
3811ab1b82
Fix the two 8bit-with-displacement effective address Calc steps.
2022-05-21 16:20:01 -04:00
Thomas Harte
f97d2a0eb9
Add DIVU/DIVS, at least as far as getting the correct numeric result.
2022-05-21 15:56:09 -04:00
Thomas Harte
2258434326
Ensure proper return addresses are calculated for JSR.
2022-05-21 14:28:44 -04:00
Thomas Harte
e46a3c4046
Implement JSR.
2022-05-21 10:29:36 -04:00
Thomas Harte
0e4cfde657
Fix MOVEM predec.
2022-05-21 08:17:39 -04:00
Thomas Harte
4bd9c36922
Fix postincrement mode.
2022-05-20 21:01:23 -04:00
Thomas Harte
256da43fe5
Fix MOVEM other than postinc and predec.
2022-05-20 20:47:54 -04:00
Thomas Harte
a818650027
Add a faulty attempt at MOVEM.
2022-05-20 18:48:19 -04:00
Thomas Harte
9d79e64f5c
Add a mere calculate effective address pathway.
...
Plus a lot of waffle to try to justify the further code duplication.
2022-05-20 16:23:52 -04:00
Thomas Harte
ee942c5c17
Fix PC-relative fetches.
2022-05-20 14:42:51 -04:00
Thomas Harte
d157819c49
Implement the various to-[SR/CCR] actions, which do a 'repeat' prefetch.
...
(which isn't exactly a repeat, at least in the SR cases, because the function code might have changed)
2022-05-20 14:29:14 -04:00
Thomas Harte
2d91fb5441
Implement MOVEP.
2022-05-20 14:22:32 -04:00
Thomas Harte
81431a5453
Attempt BTST, BCHG, BCLR and BSET.
2022-05-20 12:58:45 -04:00
Thomas Harte
b4978d1452
Implement BSR, adding one more test file to the working set.
2022-05-20 12:40:35 -04:00
Thomas Harte
45e9648b8c
Implement Bcc.
2022-05-20 12:04:43 -04:00
Thomas Harte
4327af3760
DBcc: add write-back.
2022-05-20 11:37:18 -04:00
Thomas Harte
860cc63e21
Attempt DBcc.
2022-05-20 11:32:06 -04:00
Thomas Harte
452dd3ccfd
Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.
2022-05-20 11:20:23 -04:00
Thomas Harte
e5c1621382
Add missing fallthrough, patterns for all ADDs and SUBs.
2022-05-20 07:02:02 -04:00
Thomas Harte
1ee9c585ca
Fix segue into second operand.
2022-05-19 19:38:42 -04:00
Thomas Harte
efe5a5ac26
Signal will_perform even for invalid instructions.
2022-05-19 18:50:43 -04:00
Thomas Harte
334e3ec529
Add privilege and instruction error exceptions; permit two operands to be stored.
2022-05-19 16:55:16 -04:00
Thomas Harte
282c4121d6
CLR also follows the NEGX/NEG/NOT pattern.
2022-05-19 16:30:08 -04:00
Thomas Harte
6c2eee0e44
Implement CHK, and therefore the standard exception pattern.
2022-05-19 16:27:39 -04:00
Thomas Harte
eeb6a088b8
Add a tag to avoid duplication.
2022-05-19 15:49:42 -04:00
Thomas Harte
22b63fe1f8
Add EXT, and notes to self.
2022-05-19 15:41:02 -04:00
Thomas Harte
7ef526e2d3
Fix destination decrement.
2022-05-19 15:22:59 -04:00
Thomas Harte
ce7f94559b
Add EXG, ABCD, SBCD.
2022-05-19 15:19:00 -04:00
Thomas Harte
0471decfc8
Implement the complete set of fetch addressing modes.
...
Subject to observations: (1) MOVE uses slightly custom versions of many of these for its stores; and (2) PEA and LEA need to do the calculation but not the read, so some of this will be duplicated further. It's either that or include greater conditionality on the path.
2022-05-19 15:03:22 -04:00
Thomas Harte
084d6ca11d
Simplify address handling; add perform patterns for CMP, AND, OR, EOR.
2022-05-19 12:18:47 -04:00
Thomas Harte
274902c3c1
Add to-memory write-back. Am going to reconsider usage of temporary_address_ as noted.
2022-05-19 11:23:26 -04:00
Thomas Harte
f46e7c65c5
Add AddressRegisterIndirect fetches.
2022-05-19 10:47:57 -04:00
Thomas Harte
c6c6213460
Bifurcate the fetch-operand flow.
...
Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.
2022-05-19 10:27:51 -04:00
Thomas Harte
1b87626b82
Move some way towards MOVE.
2022-05-18 21:00:10 -04:00
Thomas Harte
da9fb216b1
Remove setup_operation in favour of doing the equivalent inline.
...
... as it'll probably allow me a route to `goto` straight out of there, too. At least, if I can find a sufficiently neat macro formulation.
2022-05-18 16:45:40 -04:00
Thomas Harte
bef12f3d65
Move ExecutionState into Implementation.hpp; use goto to avoid some double switches.
...
Re: the latter, yuck. Yuck yuck yuck. But it does mean I can stop going back and forth on how to structure conditionality on effective address generation segueing into fetches without doubling up on tests.
2022-05-18 15:35:38 -04:00
Thomas Harte
aa9e7eb7a2
Codify MOVE's status somewhat, avoid reading write-only operands.
2022-05-17 16:57:33 -04:00
Thomas Harte
f3d3e588fd
Add enough of state to [sort-of] pass the first test.
...
i.e. until the processor overruns, as it is permitted to do, and can't handle the second instruction.
2022-05-17 16:51:26 -04:00
Thomas Harte
4a40581deb
Completes performance of NBCD D0.
2022-05-17 16:10:20 -04:00
Thomas Harte
eed2672db5
Add documentation, honour signal_will_perform.
2022-05-17 15:05:11 -04:00
Thomas Harte
84071ac6d0
Implement reset logic, advance as far as actually performing an NBCD on D0 (but not writing it back).
2022-05-17 14:51:49 -04:00
Thomas Harte
1a27eea46c
Establish general pattern for selecting a performance phase and obtaining operands.
2022-05-17 14:08:50 -04:00
Thomas Harte
d0b6451f02
Step gingerly on to fetching operands.
2022-05-17 08:26:35 -04:00
Thomas Harte
2147c5a5f2
Fill in missing #undefs.
2022-05-16 21:02:25 -04:00
Thomas Harte
c7aa4d8b6d
Fix state transitions.
...
Confirmed that the 68000 mk 2 now appears correctly to perform a reset.
2022-05-16 21:00:25 -04:00
Thomas Harte
e94efe887c
Switch to use of __COUNTER__.
2022-05-16 20:38:17 -04:00
Thomas Harte
3db2de7478
Works 68000 mk2 into the comparative tests.
...
... revealing that I've leant a little too hard on __LINE__.
2022-05-16 20:04:13 -04:00
Thomas Harte
345f7c3c62
Fill in just enough to attempt the reset exception, assuming DTACK rather than VPA or BERR.
2022-05-16 16:57:40 -04:00
Thomas Harte
6f6e466c08
Make a first sketch of the coroutine-esque structure I'm going to experiment with here.
2022-05-16 11:59:03 -04:00
Thomas Harte
b0518040b5
Plants the seek of a 68000 mark 2.
2022-05-16 11:44:16 -04:00
Thomas Harte
0af8660181
Remove add_pc and decline_branch in favour of operation-specific signals.
2022-05-09 16:19:25 -04:00
Thomas Harte
c61809f0c4
Add CMPAl.
2022-05-03 09:20:02 -04:00
Thomas Harte
17a2ce0464
Fix missung #undefs.
2022-05-02 21:29:46 -04:00
Thomas Harte
ef28d5512b
Annotate further.
2022-05-02 12:58:04 -04:00
Thomas Harte
fa49737538
Correct processor name.
2022-05-02 08:40:47 -04:00
Thomas Harte
8a18685902
Relocated RegisterSizes to Numeric.
2022-04-28 15:10:08 -04:00
Thomas Harte
ee625cb8a8
Minor style improvements; especially: don't assume value of NoBusProgram.
2021-12-25 14:05:38 -05:00
Thomas Harte
f20940a37b
Give Program full ownership of the sentinel value.
...
In case I want to reduce the size of this field later.
2021-12-23 16:32:21 -05:00
Thomas Harte
32e0a66610
Trust the compiler with this bit field.
2021-12-23 16:28:55 -05:00
Thomas Harte
d9598b35c2
Add some additional metrics.
2021-12-23 16:27:54 -05:00
Thomas Harte
0df8173536
Merge branch 'master' into Amiga
2021-11-24 08:58:03 -05:00
Thomas Harte
7e31658932
Remove accidental commit.
2021-10-26 21:49:32 -07:00
Thomas Harte
76767da300
Undo accidental change.
2021-10-25 21:48:19 -07:00
Thomas Harte
dc8701a929
Introduce some additional Blitter test cases.
2021-10-25 21:40:20 -07:00
Thomas Harte
313dbe05e0
Switch to more consistent inlining.
2021-09-23 22:36:15 -04:00
Thomas Harte
adf7124e2c
Eliminate 6502Base.cpp.
2021-09-23 22:33:33 -04:00
Thomas Harte
863971f944
68000: fix E alignment, expand Microcycle::apply.
2021-09-08 21:03:37 -04:00
Thomas Harte
fd70f7ad43
Attempts to make pixel content observeable.
2021-09-08 20:57:26 -04:00
Thomas Harte
5cc25d0846
Adds a further sanity assert.
2021-08-08 21:52:52 -04:00
Thomas Harte
e402e690b0
Assume and test that divide-by-zero posts the PC of the offending instruction.
2021-08-07 17:51:00 -04:00
