60 Commits

Author	SHA1	Message	Date
Thomas Harte	9e3c2b68d7	Eliminate potential future implicit conversion warnings.	2022-05-24 11:05:24 -04:00
Thomas Harte	cb77519af8	Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode.	2022-05-20 12:40:09 -04:00
Thomas Harte	452dd3ccfd	Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.	2022-05-20 11:20:23 -04:00
Thomas Harte	acb63a1307	Pull generalised DIVU/DIVS into a macro.	2022-05-15 20:01:51 -04:00
Thomas Harte	341bf2e480	Repattern DIVS after DIVU.	2022-05-15 16:54:58 -04:00
Thomas Harte	f83954f5b7	Switch to common bit-selection logic.	2022-05-13 15:08:15 -04:00
Thomas Harte	6d43576db7	Remove errant semicolon.	2022-05-12 16:21:36 -04:00
Thomas Harte	b7d1bff0c7	Eliminate branches from ABCD.	2022-05-12 15:25:01 -04:00
Thomas Harte	79c5af755f	Eliminate branches from SBCD.	2022-05-12 15:18:03 -04:00
Thomas Harte	c6d84e7e60	Use Status::FlagT pervasively.	2022-05-12 11:42:33 -04:00
Thomas Harte	192513656a	After much guesswork, fix SBCD and thereby pass flamewing tests.	2022-05-12 11:39:01 -04:00
Thomas Harte	f3c1b1f052	Name flags, remove closing underscores on exposed data fields.	2022-05-12 08:19:41 -04:00
Thomas Harte	bd61c72007	Mutate SBCD to correct values, though not yet statuses.	2022-05-12 07:22:26 -04:00
Thomas Harte	0efeea1294	Slightly improve SBCD. Not there yet though.	2022-05-12 07:07:21 -04:00
Thomas Harte	a9902fc817	Fix ABCD when the result has an invalid lower digit.	2022-05-11 16:31:27 -04:00
Thomas Harte	943c924382	Add missing: MOVE to/from USP, RESET.	2022-05-11 07:52:23 -04:00
Thomas Harte	4b97427937	Remove further magic constants.	2022-05-11 07:00:35 -04:00
Thomas Harte	c635720a09	Tidy up; provide a notification for bit-change operations.	2022-05-10 08:23:25 -04:00
Thomas Harte	f2a6a12f79	Remove further vestiges of timing.	2022-05-09 20:58:51 -04:00
Thomas Harte	7445c617bc	Start removing 68000-specific timing calculations.	2022-05-09 20:32:02 -04:00
Thomas Harte	2ca1eb4cf8	Move set_pc into the operation-specific group.	2022-05-09 16:20:15 -04:00
Thomas Harte	0af8660181	Remove add_pc and decline_branch in favour of operation-specific signals.	2022-05-09 16:19:25 -04:00
Thomas Harte	2f7cff84d9	Enable missing rotates and shifts.	2022-05-09 11:26:01 -04:00
Thomas Harte	0818fd7828	Ensure no status updates fall through the cracks.	2022-05-07 21:29:12 -04:00
Thomas Harte	bf8c97abbb	Permit TRAP, TRAPV and CHK to push the next PC rather than the current.	2022-05-07 20:32:39 -04:00
Thomas Harte	2b3900fd14	Fix LINK A7.	2022-05-07 08:15:26 -04:00
Thomas Harte	1defeca1ad	Implement RTS, RTR, RTE.	2022-05-06 12:30:49 -04:00
Thomas Harte	ac6a9ab631	Fix TAS Dn.	2022-05-06 12:23:04 -04:00
Thomas Harte	8176bb6f79	Expose issues with TST and TAS.	2022-05-06 12:18:56 -04:00
Thomas Harte	9c266d4316	Proceed to unimplemented TST.	2022-05-06 11:33:57 -04:00
Thomas Harte	607ddd2f78	Preserve MOVEM order in Operation.	2022-05-06 09:45:06 -04:00
Thomas Harte	9ab70b340c	Route MOVEM appropriately.	2022-05-05 12:42:57 -04:00
Thomas Harte	67462c2f92	Rewire MOVEP.	2022-05-05 12:27:36 -04:00
Thomas Harte	665f2d4c00	Attempts MOVEP.	2022-05-05 09:00:33 -04:00
Thomas Harte	64586ca7ba	Implement BTST/etc.	2022-05-04 20:57:22 -04:00
Thomas Harte	15c90e546f	Fix rotates and shifts to memory.	2022-05-04 19:44:59 -04:00
Thomas Harte	5d1d94848c	Take a bash at LINK and UNLK.	2022-05-04 08:26:11 -04:00
Thomas Harte	de58ec71fd	Fix EXT, SWAP.	2022-05-03 20:17:36 -04:00
Thomas Harte	052ba80fd7	Add enough wiring to complete but fail EXT and JMP/JSR.	2022-05-03 15:49:55 -04:00
Thomas Harte	af973138df	Correct decoding of Bcc.b, satisfying Bcc and BSR tests.	2022-05-03 15:32:54 -04:00
Thomas Harte	5a87506f3d	Fix Bcc, making decision that add_pc is relative to start of instruction.	2022-05-03 15:21:42 -04:00
Thomas Harte	90f0005cf2	Proceed to failing Bcc and flagging up my lack of an implementation for BSR.	2022-05-03 14:45:49 -04:00
Thomas Harte	d8b3748d24	Fix Scc size, DBcc behaviour.	2022-05-03 14:40:51 -04:00
Thomas Harte	1b224c961e	Fix Scc, add operand flags for DBcc.	2022-05-03 14:23:57 -04:00
Thomas Harte	c61809f0c4	Add CMPAl.	2022-05-03 09:20:02 -04:00
Thomas Harte	2f2d6bc08b	Correct CMPw.	2022-05-03 09:05:34 -04:00
Thomas Harte	3827ecd6d3	Proceed to complete test running.	2022-05-02 12:57:45 -04:00
Thomas Harte	73f340586d	Proceed to building, but failing tests.	2022-05-02 07:45:07 -04:00
Thomas Harte	3c26177239	Provide both compile- and run-time operation selection options.	2022-05-01 17:39:56 -04:00
Thomas Harte	52f355db24	Decision: operation is not a template parameter. Hence can use condition as fully typed.	2022-04-30 14:08:51 -04:00