Thomas Harte
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847e49ccdf
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Corrected timestamp reporting by the all-RAM Z80.
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2017-07-26 19:47:39 -04:00 |
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Thomas Harte
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81a3899381
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Adjusted the Z80 formally to communicate in terms of half cycles rather than whole.
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2017-07-26 19:42:00 -04:00 |
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Thomas Harte
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966b5e6372
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Adapted the Z80's perform_machine_cycle to return Cycles.
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2017-07-25 22:25:44 -04:00 |
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Thomas Harte
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9bff787ee1
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Corrected for the new, non-integral type.
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2017-07-24 21:05:07 -04:00 |
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Thomas Harte
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ace8e30818
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Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
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2017-07-23 22:21:39 -04:00 |
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Thomas Harte
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95a6b0f85c
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Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
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2017-06-22 21:09:26 -04:00 |
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Thomas Harte
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0e0ce379b4
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Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
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2017-06-21 20:38:08 -04:00 |
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Thomas Harte
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36e8a11505
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Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
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2017-06-21 20:32:08 -04:00 |
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Thomas Harte
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85c6fb1430
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Explained refresh cycles to the all-RAM Z80.
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2017-06-19 07:36:11 -04:00 |
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Thomas Harte
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d668879ba6
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Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
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2017-06-18 22:03:13 -04:00 |
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Thomas Harte
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e1a2580b2a
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Renamed BusOperation to MachineCycle::Operation.
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2017-06-17 21:53:45 -04:00 |
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Thomas Harte
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aed2827e7b
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Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
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2017-06-12 22:22:00 -04:00 |
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Thomas Harte
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8c41a0f0ed
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Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.
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2017-06-03 17:53:44 -04:00 |
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Thomas Harte
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3e9212aaff
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Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
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2017-06-03 17:41:45 -04:00 |
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Thomas Harte
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d14902700a
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Minor syntax and wiring fixes.
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2017-06-01 22:33:05 -04:00 |
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Thomas Harte
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494ce073b5
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Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging.
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2017-05-31 19:58:57 -04:00 |
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Thomas Harte
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2f7f11e2e5
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Added diagnosis props.
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2017-05-31 06:54:25 -04:00 |
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Thomas Harte
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5119997122
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Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
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2017-05-30 22:41:23 -04:00 |
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Thomas Harte
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da65bae86e
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Switched to supplying the bus operation by reference, go guarantee that it isn't null.
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2017-05-30 19:24:58 -04:00 |
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Thomas Harte
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d290e3d99e
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Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!)
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2017-05-29 16:35:00 -04:00 |
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Thomas Harte
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a6a4c5a936
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Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures.
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2017-05-29 15:57:27 -04:00 |
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Thomas Harte
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6b66c8f304
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Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84.
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2017-05-28 14:50:51 -04:00 |
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Thomas Harte
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6575091a78
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Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly.
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2017-05-22 21:50:34 -04:00 |
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Thomas Harte
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41d5dd8679
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Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
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2017-05-22 19:24:11 -04:00 |
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Thomas Harte
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f2aae72cc2
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Fixed the 16-bit ADCs and SBCs, added INC (HL) and DEC (HL). Zexall now enters a seemingly-infinite loop. Which is progress, at least.
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2017-05-21 20:43:36 -04:00 |
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Thomas Harte
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fe8db1873c
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Added 16-bit ADC and SBC table entries; once again extended logging.
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2017-05-21 20:32:06 -04:00 |
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Thomas Harte
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08206eea56
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This logging has outlived its usefulness for now.
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2017-05-21 09:47:53 -04:00 |
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Thomas Harte
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103c863534
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Through temporarily dramatically increased logging, fixed conditional JP.
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2017-05-20 23:03:52 -04:00 |
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Thomas Harte
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6766845e21
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Filled in most of the loads.
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2017-05-19 22:57:43 -04:00 |
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Thomas Harte
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62b432c046
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Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.
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2017-05-19 21:20:28 -04:00 |
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Thomas Harte
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11d05fb3b8
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Expanded a little on operations, added an implementation or two.
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2017-05-19 19:18:35 -04:00 |
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Thomas Harte
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5d3ebcb35a
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Made a first attempt at LD HL, (nn).
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2017-05-17 22:42:30 -04:00 |
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Thomas Harte
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17ffd604bf
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Made an attempt to get the Z80 at least as far as rejecting an opcode.
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2017-05-17 21:45:23 -04:00 |
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Thomas Harte
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7190f927b7
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Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
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2017-05-16 21:28:17 -04:00 |
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Thomas Harte
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d559d8b901
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Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
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2017-05-16 21:19:17 -04:00 |
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