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Commit Graph

8 Commits

Author SHA1 Message Date
Thomas Harte
1576b4500b Added documentation. 2017-08-13 18:27:00 -04:00
Thomas Harte
e1e9a06712 Made an attempt at format a track. 2017-08-13 18:05:19 -04:00
Thomas Harte
b0a7208cc7 Strung together a very basic version of 8272 write [/deleted] data. Lots of cases as-yet unhandled. 2017-08-13 12:50:07 -04:00
Thomas Harte
47732ffb98 Prevented the 8272 from overreading ID fields (and, by doing so, overrunning its internal buffer). Exposed the MFMController's CRC generator for inspection. 2017-08-07 12:37:22 -04:00
Thomas Harte
77da582e88 Switched the container in which events are passed to int, with the intention of subclasses extending the receivable range. 2017-08-06 12:35:20 -04:00
Thomas Harte
ffadb04761 Documented, and removed a couple of Event types that are WD-specific but had accidentally flown into here. Will need to figure out how best to expose the CRC result too, but I'm willing to let that one drop out naturally as I implement the 8272. 2017-08-06 11:36:36 -04:00
Thomas Harte
29288b690e Switched disk controllers to be instantiated explicitly in terms of cycles, created an Amstrad-specific subclass of the 8272 to record the direct programmatic availability of all disk motors bundled together, and otherwise adjusted to ensure the thing is clocked and that the motor is enabled and disabled appropriately. The 8272 is also now formally a subclass of the incoming MDM controller. 2017-08-06 09:45:16 -04:00
Thomas Harte
4d60b8801c Started trying to factor out just the PLL stream -> FM/MFM events part that is presently in the WD1770. 2017-08-05 22:26:15 -04:00