18 Commits

Author	SHA1	Message	Date
Thomas Harte	76979c8059	Add missing tests.	2022-07-26 21:47:02 -04:00
Thomas Harte	86246e4f45	Introduce partial Blitter sequencer test.	2022-07-26 21:28:12 -04:00
Thomas Harte	610c85a354	Correct test logic. ... All tests now pass.	2021-11-25 04:11:20 -05:00
Thomas Harte	012084b37b	Fix exclusive fill, sizing, eliminate ECS call-ins. ... The clock test now proceeds further, but still doesn't seem to pass.	2021-11-24 17:25:32 -05:00
Thomas Harte	8ef9a932aa	Adds inclusive fill test; fixes inclusive fills.	2021-11-07 14:26:13 -08:00
Thomas Harte	2c1f2edcf2	Introduce failing 'clock' test case. ... i.e. a few seconds of the Workbench 1.0 clock application.	2021-10-31 16:12:51 -07:00
Thomas Harte	9e6ffaad7d	Introduce test case for fill mode.	2021-10-31 14:12:26 -07:00
Thomas Harte	edb75e69cb	Implement bitplane modulos.	2021-10-29 11:29:22 -07:00
Thomas Harte	5ebc59dd1f	Introduce additional test cases.	2021-10-26 20:58:38 -07:00
Thomas Harte	4d7ce3792f	Use additional test cases.	2021-10-25 21:48:43 -07:00
Thomas Harte	dc8701a929	Introduce some additional Blitter test cases.	2021-10-25 21:40:20 -07:00
Thomas Harte	15ed4a0d09	Introduce failing test case for sector decoding.	2021-10-16 10:48:32 -07:00
Thomas Harte	6b0dd19442	Name file appropriately: the logo comes from Kickstart.	2021-10-09 08:02:15 -07:00
Thomas Harte	ad90c6b6ce	Now that this is getting close, don't stop at the first error.	2021-09-29 22:19:34 -04:00
Thomas Harte	0c998d60cb	Correct test logic for line draws that repeatedly write to the same address.	2021-09-28 21:45:55 -04:00
Thomas Harte	1dfc36f311	Flip loop, add modulo mappings.	2021-09-26 18:15:32 -04:00
Thomas Harte	19dd2f92bd	Implements test case. Failing at present, naturally.	2021-09-25 21:52:41 -04:00
Thomas Harte	acfaa016a0	Adds a capture of traffic leading up to the Workbench boot logo. ... Around which to construct a test case.	2021-09-25 18:10:07 -04:00