Thomas Harte
|
77fcf52d27
|
Purely style: remove some redundant nullptrs.
|
2021-04-19 18:53:00 -04:00 |
|
Thomas Harte
|
79c2bc1fd7
|
Put the program counter on the bus during interrupt acknowledge.
|
2021-04-19 18:43:50 -04:00 |
|
Thomas Harte
|
76370d9418
|
Merge pull request #916 from TomHarte/OffByOne
Corrects off-by-one timing errors in the ZX Spectrum.
|
2021-04-18 20:25:13 -04:00 |
|
Thomas Harte
|
7bac18bd65
|
Address bus load time is not + 1/2.
|
2021-04-18 18:41:24 -04:00 |
|
Thomas Harte
|
704737144a
|
Corrects all interrupt timing for sign and off-by-one errors.
|
2021-04-18 18:40:44 -04:00 |
|
Thomas Harte
|
2a9c73a1d3
|
Merge pull request #915 from TomHarte/SpectrumSDLOptions
Adds display of Spectrum command-line options.
|
2021-04-18 12:08:02 -04:00 |
|
Thomas Harte
|
e87e851401
|
Add a redundant but idiomatic initial value.
|
2021-04-18 11:56:22 -04:00 |
|
Thomas Harte
|
80d4846a27
|
Respond with 0xff during an interrupt acknowledge.
|
2021-04-18 11:56:00 -04:00 |
|
Thomas Harte
|
9fd53c9c91
|
Adds the ZX Spectrum to ::AllMachines.
|
2021-04-17 23:06:37 -04:00 |
|
Thomas Harte
|
53eae873d8
|
Merge pull request #913 from TomHarte/LowerModelTiming
Brings timings into line with WoS specs.
|
2021-04-16 22:45:54 -04:00 |
|
Thomas Harte
|
93422f4b1c
|
Brings timings into line with WoS specs.
|
2021-04-16 22:40:51 -04:00 |
|
Thomas Harte
|
06cedb2e50
|
Merge pull request #912 from TomHarte/128kDecoding
Corrects Spectrum 128kb partial decoding.
|
2021-04-16 22:02:25 -04:00 |
|
Thomas Harte
|
7fdb1d848b
|
Corrects Spectrum 128kb partial decoding.
|
2021-04-16 21:54:52 -04:00 |
|
Thomas Harte
|
246fd9442f
|
Merge pull request #911 from TomHarte/48kbSpectrum
Adds the 48kb and 128kb Spectrums.
|
2021-04-15 22:25:07 -04:00 |
|
Thomas Harte
|
eb99a64b29
|
Adds new Spectrum models to Qt UI.
|
2021-04-15 22:20:34 -04:00 |
|
Thomas Harte
|
d7954a4cb1
|
Tweaks timing a little.
|
2021-04-15 21:51:49 -04:00 |
|
Thomas Harte
|
ef636da866
|
Attempts 48/128kb floating bus behaviour.
|
2021-04-15 21:19:21 -04:00 |
|
Thomas Harte
|
fa18b06dbf
|
Correct get_floating_value to be consistent in out-of-bounds behaviour.
|
2021-04-15 21:13:36 -04:00 |
|
Thomas Harte
|
349b9ce502
|
Don't post contended accesses other than on the +2a/+3.
Those machines have an actual latch for this stuff, the others don't.
|
2021-04-15 21:13:06 -04:00 |
|
Thomas Harte
|
b2cf121410
|
Regresses default to the more-compatible +2.
|
2021-04-15 19:31:45 -04:00 |
|
Thomas Harte
|
71cf63bd35
|
Corrects internal cycle contention.
|
2021-04-15 19:17:11 -04:00 |
|
Thomas Harte
|
d1bb3aada4
|
Attempts to complete the in-machine application of contention.
|
2021-04-15 18:57:34 -04:00 |
|
Thomas Harte
|
b4214c6e08
|
Blocks off the AY from inputs in 48kb mode.
|
2021-04-15 18:04:16 -04:00 |
|
Thomas Harte
|
f5c7746493
|
Extends fast loading support to the just-introduced models.
|
2021-04-15 17:31:42 -04:00 |
|
Thomas Harte
|
f10ec80153
|
Gets started on different video timings.
|
2021-04-14 22:23:27 -04:00 |
|
Thomas Harte
|
0af405aa46
|
Starts working in the 48kb and 128kb Spectrums.
|
2021-04-14 21:37:10 -04:00 |
|
Thomas Harte
|
cf481effa6
|
Merge pull request #910 from TomHarte/FastContention
Establishes that the 48/128kb contention patterns can be derived from my partial machine cycles alone.
|
2021-04-14 20:21:52 -04:00 |
|
Thomas Harte
|
a1511f9600
|
Establishes that the 48/128kb contention patterns can be derived from my partial machine cycles alone.
|
2021-04-14 20:15:40 -04:00 |
|
Thomas Harte
|
325e2b3941
|
Merge pull request #902 from TomHarte/Z80Lines
Spell out, test and correct Z80 bus activity.
|
2021-04-13 22:22:26 -04:00 |
|
Thomas Harte
|
7017324d60
|
r_step is obsolete now that I know that [DD/FD]CB don't have a refresh cycle.
|
2021-04-13 22:17:30 -04:00 |
|
Thomas Harte
|
deb5d69ac7
|
Consolidates macros.
|
2021-04-13 22:11:28 -04:00 |
|
Thomas Harte
|
68a04f4e6a
|
Adds IN/OUT I/D [R] to complete tests.
|
2021-04-13 22:00:24 -04:00 |
|
Thomas Harte
|
0d61902b10
|
Adds CP[I/D/IR/DR] tests.
|
2021-04-13 20:03:11 -04:00 |
|
Thomas Harte
|
3eec210b30
|
Adds LDI/LDD/LDIR/LDDR tests.
|
2021-04-13 20:00:29 -04:00 |
|
Thomas Harte
|
5998f3b35b
|
Corrects LD[I/D/IR/DR] timing.
Macro cleanup to come.
|
2021-04-13 20:00:18 -04:00 |
|
Thomas Harte
|
869567fdd9
|
Corrects EX (SP), HL breakdown.
|
2021-04-13 19:45:48 -04:00 |
|
Thomas Harte
|
2e70b5eb9f
|
Advances to EX (SP), HL, leaving only [LD/CP/IN/OT][I/D]{R}.
|
2021-04-13 19:45:29 -04:00 |
|
Thomas Harte
|
8a3bfb8672
|
Adds an IN/OUT test.
|
2021-04-13 17:55:51 -04:00 |
|
Thomas Harte
|
06f1e64177
|
Advances to IO.
|
2021-04-12 21:41:20 -04:00 |
|
Thomas Harte
|
b42780173a
|
Establishes that there really is no Read4 and Read4Pre distinction.
Will finish these unit tests, then clean up.
|
2021-04-12 20:54:10 -04:00 |
|
Thomas Harte
|
36c8821c4c
|
Reaches the halfway point in tests.
|
2021-04-12 17:29:03 -04:00 |
|
Thomas Harte
|
947de2d54a
|
Switches five-cycle read to a post hoc pause.
|
2021-04-12 17:17:08 -04:00 |
|
Thomas Harte
|
9347fe5f44
|
Advances to next failing test: LD (ii+n), n.
|
2021-04-12 17:11:58 -04:00 |
|
Thomas Harte
|
e82367def3
|
Switches to test-conformant behaviour for (IX/IY+n) opcode fetches.
|
2021-04-11 23:01:00 -04:00 |
|
Thomas Harte
|
9cde7c12ba
|
Shifts responsibility for refresh into the fetch-decode-execute sequence.
|
2021-04-11 22:50:24 -04:00 |
|
Thomas Harte
|
015556cc91
|
Switch (ii+n) to Read4Pre.
|
2021-04-11 10:26:14 -04:00 |
|
Thomas Harte
|
47c5a243aa
|
Restructures, the better to explore errors.
|
2021-04-10 21:32:42 -04:00 |
|
Thomas Harte
|
070e359d82
|
Introduces failing test for BIT b, (ii+n).
|
2021-04-10 18:00:23 -04:00 |
|
Thomas Harte
|
b397059d5e
|
Moves read time in Read4Pre.
|
2021-04-10 17:54:20 -04:00 |
|
Thomas Harte
|
400f54e508
|
Introduces failing test for bit b, (hl).
|
2021-04-10 12:04:48 -04:00 |
|