1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-07 04:05:30 +00:00
Commit Graph

10 Commits

Author SHA1 Message Date
Thomas Harte
f42655a0fc Promote DigitalPhaseLockedLoop to a template, simplify to O(1) add_pulse. 2020-01-12 17:25:21 -05:00
Thomas Harte
0b771ce61a Removes all instances of the copyright symbol. 2018-05-13 15:19:52 -04:00
Thomas Harte
7b5f93510b Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests. 2017-07-16 20:55:57 -04:00
Thomas Harte
fa7c64bb5d Eventually reached an implementation of ADC that continues to satisfy all the formalised unit tests while also satisfying the manual BCDTest, that I need to find a way to formalise. I fixed the unit tests for Swift 3 while here, and attempted to do some unrelated NIB stuff with no real success. 2016-10-03 22:03:39 -04:00
Thomas Harte
7c65c69e0f Migrated to Swift 3. 2016-09-15 22:12:12 -04:00
Thomas Harte
015cea494d Switched to a much-more straightforward PLL. I think I'm just fiddling now rather than moving forwards. Probably time to move on? 2016-07-28 11:32:14 -04:00
Thomas Harte
e061e849d4 Had a second bash at the PLL. Probably I should read some of the literature. 2016-07-27 16:24:24 -04:00
Thomas Harte
74817f6664 With a history of three pulses, this can track up a 10% sine variation in a 1010101 stream. So I guess this'll do for now? 2016-07-14 19:54:48 -04:00
Thomas Harte
ac1bc588dd Improved factoring and increased window of testing, causing both the fast and slow tests to show framing errors. 2016-07-14 07:12:02 -04:00
Thomas Harte
d1fe07f14d Added test of perfect DPLL input timing. 2016-07-12 21:42:23 -04:00