Thomas Harte
|
7b234078ae
|
Implemented EX DE, HL and shuffled to allow instruction pages.
|
2017-05-20 17:04:25 -04:00 |
|
Thomas Harte
|
add02a7897
|
Added LD (nn), A, and reduced double logging to single for now.
|
2017-05-19 23:13:28 -04:00 |
|
Thomas Harte
|
19167df692
|
Consolidated and filled in AND and XOR.
|
2017-05-19 23:03:34 -04:00 |
|
Thomas Harte
|
6766845e21
|
Filled in most of the loads.
|
2017-05-19 22:57:43 -04:00 |
|
Thomas Harte
|
bc3b5f3e35
|
Added 16-bit INCs and DECs. Which don't set flags, so are easy.
|
2017-05-19 22:13:36 -04:00 |
|
Thomas Harte
|
5fe23113ec
|
Moved RET to the correct place, implemented POP AF.
|
2017-05-19 22:03:12 -04:00 |
|
Thomas Harte
|
c55e1c1d17
|
Implemented POP and therefore RET; corrected timing of PUSH.
|
2017-05-19 21:59:45 -04:00 |
|
Thomas Harte
|
d910405648
|
Added enough infrastructure to be able to react to the two CP/M calls this cares about.
|
2017-05-19 21:53:39 -04:00 |
|
Thomas Harte
|
62b432c046
|
Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.
|
2017-05-19 21:20:28 -04:00 |
|
Thomas Harte
|
eae1f78221
|
Implemented the main page pushes.
|
2017-05-19 19:28:38 -04:00 |
|
Thomas Harte
|
11d05fb3b8
|
Expanded a little on operations, added an implementation or two.
|
2017-05-19 19:18:35 -04:00 |
|
Thomas Harte
|
58efca835f
|
Sought to add a further opcode.
|
2017-05-18 22:53:43 -04:00 |
|
Thomas Harte
|
99f2060fc1
|
Further improved macros.
|
2017-05-18 22:11:54 -04:00 |
|
Thomas Harte
|
5d3ebcb35a
|
Made a first attempt at LD HL, (nn).
|
2017-05-17 22:42:30 -04:00 |
|
Thomas Harte
|
509d011fbe
|
Implemented JP, my first Z80 operation.
|
2017-05-17 22:31:41 -04:00 |
|
Thomas Harte
|
17ffd604bf
|
Made an attempt to get the Z80 at least as far as rejecting an opcode.
|
2017-05-17 21:45:23 -04:00 |
|
Thomas Harte
|
21d0602305
|
Restored the all RAM 6502's lack of power-on reset.
|
2017-05-17 21:43:40 -04:00 |
|
Thomas Harte
|
1378ab7278
|
Ensured initial program counter and stack pointer are correct for Zexall, fixed the Z80 to use a compile-time polymorphic call for bus access.
|
2017-05-17 07:36:06 -04:00 |
|
Thomas Harte
|
87a021ec2d
|
Made further attempt to get as fas as having the Z80 attempt to do something.
|
2017-05-16 22:19:40 -04:00 |
|
Thomas Harte
|
7190f927b7
|
Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
|
2017-05-16 21:28:17 -04:00 |
|
Thomas Harte
|
d559d8b901
|
Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
|
2017-05-16 21:19:17 -04:00 |
|
Thomas Harte
|
50bb4f0142
|
There's finally a loop in here, at least.
|
2017-05-15 22:25:52 -04:00 |
|
Thomas Harte
|
7da51602d5
|
Moved flush, added run_for_cycles, which does nothing right now.
|
2017-05-15 07:59:21 -04:00 |
|
Thomas Harte
|
5152517887
|
Added the boilerplate stuff necessary to query registers.
|
2017-05-15 07:55:53 -04:00 |
|
Thomas Harte
|
eb8a2de5d6
|
Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.
|
2017-05-15 07:38:59 -04:00 |
|
Thomas Harte
|
f2a1a906ff
|
Adapted what negligible amount there is of the z80 as per the new CPU namespace.
|
2017-05-14 22:15:16 -04:00 |
|
Thomas Harte
|
0808e9b6fb
|
Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.
|
2017-05-14 22:08:15 -04:00 |
|
Thomas Harte
|
b81a2cc273
|
First tentative steps towards adding a Z80 implementation.
|
2017-05-14 17:46:41 -04:00 |
|
Thomas Harte
|
defec2c9b0
|
Fixed: operation reads now fulfil the promise of seeding the value to be read with 0xff.
|
2017-03-26 20:56:27 -04:00 |
|
Thomas Harte
|
e01f3f06c8
|
Completed curly bracket movement.
|
2017-03-26 14:34:47 -04:00 |
|
Thomas Harte
|
55ce851bb2
|
Fixed types of the 8k cartridges, ensured the 6502 starts without an IRQ request history.
|
2017-03-18 17:04:01 -04:00 |
|
Thomas Harte
|
36b58d03b7
|
Formalised read bus value guarantee from the 6502, fixed missing clock signal wiring on the Atari cartridge class, reintroduced CommaVid support.
|
2017-03-18 14:46:46 -04:00 |
|
Thomas Harte
|
14a76af0d3
|
Started trying to float out bus control to cartridges.
|
2017-03-17 20:28:07 -04:00 |
|
Thomas Harte
|
5be22e2f8d
|
Switched to suffix underscores and underscores in general for instance variables.
|
2016-12-03 11:38:53 -05:00 |
|
Thomas Harte
|
7ad44f5152
|
Flipped order of conditional so as negligibly to improve prediction.
|
2016-10-31 22:17:18 -04:00 |
|
Thomas Harte
|
2452a3104f
|
Corrected test: hitting zero is sufficient. No need to cross it.
|
2016-10-30 20:24:30 -04:00 |
|
Thomas Harte
|
9309be229c
|
Moved cycle count test down to the only places where it may actually yield a different result.
|
2016-10-30 20:13:44 -04:00 |
|
Thomas Harte
|
a106018680
|
Fixed initial state: interrupt flag is initially low.
|
2016-10-28 21:22:03 -04:00 |
|
Thomas Harte
|
613b5b3f98
|
Switched to inverse storage of the interrupt flag so as to reduce logical burden when storing IRQ line history.
|
2016-10-28 20:52:43 -04:00 |
|
Thomas Harte
|
4408c60ef7
|
This too should continue, not break, since it doesn't schedule a memory access.
|
2016-10-27 18:32:21 -04:00 |
|
Thomas Harte
|
534b3d085d
|
Improved test reporting, attempted to resolve timing errors just introduced (i.e. to differentiate break/continue where a cycle may or may not be spent).
|
2016-10-27 08:41:44 -04:00 |
|
Thomas Harte
|
f84b66a5f4
|
Made an attempt to fix wake-from-WAIT.
|
2016-10-25 19:06:46 -04:00 |
|
Thomas Harte
|
4b18c76b84
|
Introduced a bifurcation between break and continue to signify whether a bus access takes place, necessitating a shift in the location of the bus access but allowing the conditional to be dropped. Need to test.
|
2016-10-25 18:45:53 -04:00 |
|
Thomas Harte
|
c253a4258f
|
Made minor restructuring changes, slightly to reduce number of conditionals per operation and to drop a big hint to the optimiser.
|
2016-10-25 18:34:24 -04:00 |
|
Thomas Harte
|
fa7c64bb5d
|
Eventually reached an implementation of ADC that continues to satisfy all the formalised unit tests while also satisfying the manual BCDTest, that I need to find a way to formalise. I fixed the unit tests for Swift 3 while here, and attempted to do some unrelated NIB stuff with no real success.
|
2016-10-03 22:03:39 -04:00 |
|
Thomas Harte
|
5d40d70c92
|
Fixed 6560 addressing error, added an autotyper for Vic disks (more work potentially needed), fixed semantics for testing whether a 6502 is about to reset.
|
2016-08-01 10:32:32 -04:00 |
|
Thomas Harte
|
740ea0b7e2
|
Added overflow-flag setting logic and ensured disk ROM gets through regardless of ROM/disk installation order.
|
2016-07-31 19:33:18 -04:00 |
|
Thomas Harte
|
1baf21827c
|
Since the ROM is well disassembled, let's actually try to be a 1541 first.
|
2016-07-06 22:17:32 -04:00 |
|
Thomas Harte
|
41809d4597
|
Made an attempt at NMI usurption of IRQ/BRK.
|
2016-06-29 20:59:45 -04:00 |
|
Thomas Harte
|
c02226bc41
|
Ensured stack pointer goes the right way upon reset.
|
2016-06-29 20:42:26 -04:00 |
|