| 
							
							
								 Thomas Harte | 9447aa38be | Removes debugging printf. | 2020-09-22 22:13:54 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 022ec20e75 | Tries to add semantic meaning to the various auxiliary control fields. To consider: decoding at set? | 2020-09-22 20:50:39 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 41f69405d8 | Don't decrement timer 1 from the system clock when in PB6 mode. TODO: rest of PB6 mode. | 2020-09-21 22:39:49 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 8e242eea54 | Ensures timer-linked PB7 output is actually output. | 2020-09-20 15:03:26 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 703065a0a5 | Takes a run at timer-linked PB7 output behaviour. Seemingly sufficiently to pass the VICE test (which I've transcribed), though with some guesswork. | 2020-09-20 14:51:59 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | e807a462a1 | My new reading is that only a write to the counter should affect the interrupt flag. | 2020-09-17 21:31:29 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 18790a90ae | Ensures timer 2 doesn't use timed behaviour when in pulse mode. | 2020-09-17 21:09:32 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 21afc70261 | Adds formal data-sheet names. | 2020-09-17 19:00:46 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 25996ce180 | Further doubles down on construction syntax for type conversions. | 2020-05-09 23:00:39 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 31c6faf3c8 | Adds a bunch of consts. | 2020-05-09 21:23:52 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | c1bae49a92 | Standardises on readandwritefor bus accesses.Logic being: name these things for the bus action they model, not the effect they have. | 2020-01-05 13:40:02 -05:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 1c154131f9 | Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate. | 2019-10-29 22:36:29 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | a43ada82b2 | Experiments with a JustInTimeActor in the Master System. | 2019-07-29 15:38:41 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | ee8d853fcb | Ensures you can't get a phase 2 for free with run_for(0). | 2019-07-17 14:20:27 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 245e27c893 | Solidifies belief that the shift register bit is cleared on read/write. | 2019-07-08 16:45:15 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 28de629c08 | Fixes the 6522 sufficiently to fix keyboard input. | 2019-07-08 15:29:34 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 210bcaa56d | Introduces an initial shift unit test, and makes it pass. | 2019-07-07 22:13:36 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 9230969f43 | Corrects enough of the 6522 and Keyboard to get an initial command seemingly working. | 2019-06-10 09:28:27 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 0e16c67805 | Improves shift register connection, towards having the keyboard function properly. It now seems not to receive a command terminator, but is at least getting a command. | 2019-06-08 23:04:55 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | abe55fe950 | Adds Timer 1 toggling of PB7. | 2019-06-03 15:39:20 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 723137c0d4 | With some time additions to the 6522, starts wiring in Macintosh audio. The audio buffer is also the disk motor buffer, so this is preparatory to further disk work. | 2019-06-01 14:39:40 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 8293b18278 | Adds a TODO on what I think might be an incorrect implementation? | 2019-05-08 15:06:40 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 2ba0364850 | Adds the shift register interrupt. | 2019-05-08 15:02:07 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 2e7bc0b98a | Attempts the shift register. | 2019-05-08 14:54:40 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 8278809383 | Attempts to get more rigorous on communicating outward control line changes. | 2019-05-08 13:33:22 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 4367459cf2 | Takes a first go at handshake and pulse modes. | 2019-05-08 12:48:29 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 254132b83d | Eliminates 6522Base in pursuit of working handshake modes. Specifically: this means that the places from which the BusHandler may be called are more numerous. | 2019-05-08 12:35:17 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 7e6d4f5a3e | Adds emulation of the real-time clock. | 2019-05-08 00:12:19 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | d97348dd38 | Eliminates dangling uses of printf. | 2019-03-02 18:07:05 -05:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 0b771ce61a | Removes all instances of the copyright symbol. | 2018-05-13 15:19:52 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | bc464e247f | The 1540 and, by extension, the Vic-20 are now activity sources. | 2018-05-11 22:24:33 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | edb9fd301c | Begins this project's conversion to functional-style casts. | 2017-10-03 22:04:15 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 7fd6699e0b | Corrects comment indentation. | 2017-09-05 21:15:15 -04:00 |  | 
			
				
					| 
							
							
								 Thomas Harte | 24b3faa427 | Deconstitutes the 6522 into component parts, templated and non-templated. Adjusts the Oric, Vic-20 and C-1540 accordingly, albeit with the quickest possible solutions. | 2017-09-04 14:26:04 -04:00 |  |