6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-12-27 01:31:42 +00:00
Code Issues Projects Releases Wiki Activity
4,187 Commits 7 Branches 121 Tags 500 MiB
858721a7a5
Commit Graph

554 Commits

Author SHA1 Message Date
Thomas Harte
858721a7a5 Added left border hiding. 2018-10-04 18:52:23 -04:00
Thomas Harte
89db1d6a6a Switches to a more accurate means of left-padding. 2018-10-04 18:44:49 -04:00
Thomas Harte
de4e5c40aa Implements horizontal scrolling lock. 2018-10-03 23:28:33 -04:00
Thomas Harte
05248ab990 Starts to reimplement Master System output. 2018-10-03 23:13:21 -04:00
Thomas Harte
252f47a425 Ensures no pixel output on line one before end, and adds a temporary debugging test. 2018-10-02 22:59:20 -04:00
Thomas Harte
be52b31b5c Attempts fully to revive text mode. 2018-10-02 22:05:58 -04:00
Thomas Harte
23c3fa6993 Fixed: it's the SMS that has 8 sprites, not text mode (which has none). 2018-10-02 22:01:43 -04:00
Thomas Harte
499fc62187 Sets things up for implementation of the inner mode-specific logic. 2018-10-02 21:58:09 -04:00
Thomas Harte
1dd5272190 Ensures real-time output of all areas, to ensure proper palette response. 2018-10-02 21:18:28 -04:00
Thomas Harte
5361120353 Restores a stable frame. 2018-10-02 21:05:30 -04:00
Thomas Harte
60bab8fdf1 Starts to reformulate TMS collection as coroutines. 
For the time being, thereby breaks all video. A static screen of the border colour is all you'll see.
 2018-10-01 23:03:17 -04:00
Thomas Harte
91aa8f9295 Amps up colour content a little. 2018-09-30 20:47:26 -04:00
Thomas Harte
23191efc05 Starts writing and referring to colour RAM for colours. 2018-09-29 19:50:13 -04:00
Thomas Harte
0d8af010b6 Takes a stab at tile reversal and vertical scrolling. 2018-09-28 22:37:10 -04:00
Thomas Harte
7b9bb772ca Corrected to give a not-exactly-indexed-correctly approximation of what's on display. 2018-09-28 21:03:51 -04:00
Thomas Harte
f7e211c245 Makes first attempt to put something vaguely like the Master System tile map on screen. 2018-09-28 20:39:14 -04:00
Thomas Harte
35c2e74af8 Attempts to establish a coroutine-ish structure for access patterns. 
The Master System mode, inevitably, is the test case.
 2018-09-27 22:33:41 -04:00
Thomas Harte
19482a563f Attempts to explicitly make room for the SMS VDP mode. 2018-09-27 21:22:57 -04:00
Thomas Harte
9683c8f664 Advances towards the Master System actually receiving interrupts. 2018-09-23 15:58:23 -04:00
Thomas Harte
e7f4babf41 Starts taking steps towards SMS/GG and V9938/9958 support. 
Specifically: routine namespace stuff, plus the intention to move to a table-based operation+cost version of timing. Reordering works fine for the TMS, and probably would also for the SMS/GG, but it'd be problematic with the command engine of the V9938/9958 and maintaining a consistent set of code is easier.
 2018-09-17 22:59:16 -04:00
Thomas Harte
a38639d099 Eliminates the concept of an iCoordinate. 
Real-life precision appears not to support the idea of sub-sample pixel storage.
 2018-09-12 20:05:39 -04:00
Thomas Harte
31b048f966 Ensures all bools start in a valid state. 2018-09-10 22:21:03 -04:00
Thomas Harte
7b9c1bb69c Makes minor layout improvements. 2018-09-09 21:02:31 -04:00
Thomas Harte
70c4d6b9b3 Adds a one second delay between controller and drive motor off. 2018-08-03 21:13:18 -04:00
Thomas Harte
98bb5bd9f1 Ensures flux bits are observable for two cycles rather than one; it should be 1us. 2018-07-31 23:01:11 -04:00
Thomas Harte
92065813ef Ensures only the first 8px of sprites is output in 8x8 mode. 
Also adds a little extra documentation.
 2018-07-15 22:21:29 -04:00
Thomas Harte
cd464fc7de Corrects status logging. 2018-06-26 20:53:08 -04:00
Thomas Harte
df8c896193 Removes unused state and implements AND output readback. 2018-06-26 19:31:16 -04:00
Thomas Harte
59f8eeb05a Ensures the AY goes high impedance when not in read mode. 2018-06-25 20:48:24 -04:00
Thomas Harte
5ab4cfee84 Factors out repeated hex-size setting. 2018-06-21 19:27:54 -04:00
Thomas Harte
a9eb0d02c6 Returns sanity to 8272 logging. 2018-06-20 23:02:32 -04:00
Thomas Harte
adca862166 Finally makes an initial pass at logging macros. 2018-06-18 22:37:19 -04:00
Thomas Harte
dde9b73a22 Creates the through-path that will be necessary for RWTS acceleration. 2018-06-09 12:51:53 -04:00
Thomas Harte
076fa55651 Corrects: flux set is no-flux incoming. 
This restores good sleeping behaviour.
 2018-06-03 08:11:17 -04:00
Thomas Harte
1a9cea050e Minor: ensure AY registers *read* as 0 from reset, as well as being 0. 2018-06-01 19:48:42 -04:00
Thomas Harte
35e84ff1a8 Corrects NTSC quadrature phase. 2018-05-31 21:40:46 -04:00
Thomas Harte
75f9e3caeb Resolves incorrect bracketing. 2018-05-28 17:48:35 -04:00
Thomas Harte
928aab13dc Introduces more granular clocking announcements to the Disk II. 
As well as making it accept the clock rate it'll actually receive, to supply to the drives, so that they spin at the proper speed.
 2018-05-28 17:19:29 -04:00
Thomas Harte
db8d8d8404 Commutes Sleeper to ClockingHint::Source, making state more granular. 2018-05-27 23:17:06 -04:00
Thomas Harte
086b801c29 Mildly rearranges to avoid unnecessary call. 2018-05-22 21:50:07 -04:00
Thomas Harte
e482929da8 Enhances the Disk II's ability to sleep. 
Also enables Disk II sleep observation in the Oric.
 2018-05-19 23:15:28 -04:00
Thomas Harte
ed06533e60 Implements write support out of the Disk II. 2018-05-18 22:07:58 -04:00
Thomas Harte
7b7beb13a3 Eliminates the fiction of setting and getting registers. 
The Disk II seems lower level than that; it will read the data bus whenever it likes, it is the programmer's responsibility to keep up with that. It also reserves the right not to load the bus regardless of whether it receives a read or write access.
 2018-05-17 21:39:11 -04:00
Thomas Harte
c46007332a Switches to returning the shift register contents on every even read. 2018-05-17 20:18:34 -04:00
Thomas Harte
908d3b0ee5 Slightly wrong as to the details, but gets the controller trying to output. 
At an initial look, I think the shift register should end up on the data bus for all odd accesses. Need to investigate more thoroughly.
 2018-05-16 22:37:22 -04:00
Thomas Harte
8a031b1137 Eliminates 'data' register as it doesn't exist; rejigs state machine command set. 2018-05-16 22:09:59 -04:00
Thomas Harte
1aba9f807e Ensures proper upward propagation of sleeping from first start. 2018-05-16 22:07:54 -04:00
Thomas Harte
4c49963988 Switches to proper handling of the motor control and write protection. 
Per Understanding the Apple II the drive looks write protected  while phase 1 is enabled.
 2018-05-16 21:44:09 -04:00
Thomas Harte
ad9b0cd4e3 Eliminates all endashes. 2018-05-13 15:43:03 -04:00
Thomas Harte
5d6b5d9f10 Eliminates all emdashes in cross-platform code. 2018-05-13 15:34:31 -04:00