Thomas Harte
fba210f7ce
Corrects MOVE.l Dn, (An)[+].
2019-04-15 09:30:49 -04:00
Thomas Harte
52e33e861c
Starts to introduce the QL as a second source for 68000 testing.
...
It's advantageous over the ST in that a commented disassembly of the ROM is available.
2019-04-14 22:15:09 -04:00
Thomas Harte
2ba66c4457
Corrects MOVEA, adds extra test safeguards.
2019-04-12 16:10:17 -04:00
Thomas Harte
06a2f59bd0
Implements DBcc.
2019-04-06 23:21:01 -04:00
Thomas Harte
0af57806da
Adds a hard-coded value sufficient to advance in TOS startup.
2019-04-06 20:00:34 -04:00
Thomas Harte
73e1c8c780
Corrects now-unimplemented ADD/SUB.
2019-04-03 19:43:54 -04:00
Thomas Harte
2c5ff9ada0
Switches to running the real TOS, at least temporarily, and enables better testing.
2019-03-31 22:27:57 -04:00
Thomas Harte
b0b2798f39
Updates to track Swift.
2019-03-27 21:25:51 -04:00
Thomas Harte
47359dc8f1
Adds tests for MOVE.l (An), Dn, and thereby correct their implementation.
2019-03-23 21:41:47 -04:00
Thomas Harte
d7c3d4ce52
Adds test for MOVEA.w (0x1000), A1 and fixes implementation thereof.
2019-03-22 23:27:48 -04:00
Thomas Harte
87420881c8
Extends to a failing test.
2019-03-21 23:32:03 -04:00
Thomas Harte
fdc598f2e1
Starts MOVE tests; in pursuit of which talks the 68000 into obeying run lengths.
2019-03-21 22:30:41 -04:00
Thomas Harte
0d7bbdad54
Begins a basic get/set state API, allowing some actual unit tests, implying an ABCD fix.
2019-03-17 21:57:00 -04:00
Thomas Harte
388d808536
Switches to providing UDS and LDS implicitly via address.
...
Also makes sure that the difference between a non-data cycle that starts without the address strobe active and one that starts with it active can be discerned.
2019-03-16 17:54:58 -04:00
Thomas Harte
720aba3f2d
Adds an implementation of SBCD and slightly neatens syntax for building programs.
2019-03-14 21:22:02 -04:00
Thomas Harte
f9101de956
This might very well be the 68000's first real gasp: performing an ABCD.
2019-03-14 19:32:15 -04:00
Thomas Harte
9e8928aad9
Implements as much as I currently care about of the Atari ST memory map.
2019-03-11 22:47:37 -04:00
Thomas Harte
89c71f9119
Introduces EmuTOS, and starts constructing test cases around it.
2019-03-10 18:40:12 -04:00
Thomas Harte
a4f6db6719
Removes ArrayBuilderTests as the ArrayBuilder is long gone. Disables TIA tests for now.
2019-03-10 18:07:23 -04:00
Thomas Harte
6a93d2d006
Corrects some minor spaces-instead-of-tabs errors.
2019-01-24 22:59:03 -05:00
Thomas Harte
ee89be6730
Removes many stray spaces.
2018-11-23 22:32:32 -05:00
Thomas Harte
a8645f80bf
Introduces 'non-exclusive' emulator-space keyboards.
...
i.e. sets of keys that don't amount to an entire keyboard in the modern sense. Experimentally used by the Master System for its reset key.
2018-10-24 21:59:30 -04:00
Thomas Harte
c07f9fed99
Corrects test and implementation to pass the exhaustive VDP interrupt prediction test.
2018-10-21 18:42:49 -04:00
Thomas Harte
616777517d
Makes the failing test more communicative, in the hope of more easily debugging errors.
2018-10-21 14:35:44 -04:00
Thomas Harte
b3f1677da5
Introduces new failing test for rational continuous interrupt prediction.
2018-10-21 13:59:14 -04:00
Thomas Harte
725b364bbc
Improves testing; now tests for time to the first interrupt.
2018-10-20 18:25:55 -04:00
Thomas Harte
acdc84e08c
Improves test slightly, and fixes line interrupt reload value setting.
2018-10-09 22:14:35 -04:00
Thomas Harte
c128ddb549
Introduces a first unit test for line interrupts and corrects backup behaviour.
2018-10-09 21:49:21 -04:00
Thomas Harte
fc84ae611e
Resolves various instances of spaces in place of tabs.
2018-09-09 20:33:56 -04:00
Thomas Harte
ddf45a0010
Ensures NMI and RST reset D on 65C02s.
2018-08-14 19:49:14 -04:00
Thomas Harte
261fb3d4f8
Implements proper test for ADC/SBC 65C02 NZ, though not yet the proper timing.
...
This gets Klaus Dorman's test to pass.
2018-08-10 22:42:35 -04:00
Thomas Harte
b63e0cff72
Improves has-completed test.
2018-08-10 22:27:01 -04:00
Thomas Harte
5d6e479338
Implements RMB and SMB, and fixes SBC (zero).
2018-08-10 22:13:51 -04:00
Thomas Harte
90094529a5
Implements TSB and TRB, and adds the extra BIT instructions.
2018-08-10 22:04:45 -04:00
Thomas Harte
aed4c0539e
Implements STZ.
2018-08-10 21:17:02 -04:00
Thomas Harte
95164b79c9
Attempted implementation of (zp) addressing mode.
2018-08-09 21:51:14 -04:00
Thomas Harte
bb680b40d8
Implements the 65C02's JMPs.
2018-08-08 22:26:57 -04:00
Thomas Harte
e3f6da6994
Implements the 65C02 NOPs.
2018-08-08 20:00:14 -04:00
Thomas Harte
32338bea4d
Implements BRA.
2018-08-06 22:37:30 -04:00
Thomas Harte
1a44ef0469
Introduces Klaus Dorman's 65C02 tests. All failing.
2018-08-06 21:48:43 -04:00
Thomas Harte
ebce9a2e51
Fixes test target.
2018-08-06 21:15:13 -04:00
Thomas Harte
abca38a548
Makes an initial removal of PCMPatchedTrack. Farewell, old friend.
2018-07-01 22:49:57 -04:00
Thomas Harte
853261364e
Generalised CRC generation and created specific subclasses for the CCITT CRC16 and CRC32.
2018-05-23 22:21:57 -04:00
Thomas Harte
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
Thomas Harte
05e31d7594
Mutates testComplicatedTrackSeek into an actual test.
...
Which frustratingly passes.
2018-05-01 19:52:12 -04:00
Thomas Harte
f4097290c2
Made various corrections following a quick for-loop constness audit.
2018-04-30 22:23:57 -04:00
Thomas Harte
b32538f3c8
Adds an additional test.
2018-04-30 22:05:44 -04:00
Thomas Harte
e7618bb32e
Corrects types (/chickens out).
2018-04-30 22:04:05 -04:00
Thomas Harte
e599e65087
Switches to use of the TargetList typedef wherever possible.
2018-04-14 19:46:38 -04:00
Thomas Harte
389979923e
Performs update to and satisfaction of Xcode 9.3's preferred warnings.
2018-03-30 10:25:01 -04:00
Thomas Harte
f0f9d5a6af
Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour.
2018-03-08 20:30:22 -05:00
Thomas Harte
fdef914137
Corrects test target regression.
2018-03-06 18:32:21 -05:00
Thomas Harte
66faed4008
Gives MachineForTargets complete responsibility for initial machine state.
2018-01-25 18:28:19 -05:00
Thomas Harte
21efb32b6f
Integrates the static and nascent dynamic analyser namespaces.
2018-01-24 21:48:44 -05:00
Thomas Harte
ed564cb810
Implements the main four cartridge banking schemes.
...
Slightly proof of concept for now.
2018-01-04 22:18:18 -05:00
Thomas Harte
c8367a017f
Cleans up test and makes attempt to factor in cartridge type popularity.
2018-01-01 21:21:05 -05:00
Thomas Harte
344a12566b
Tweaks a couple of expected cartridge types.
2018-01-01 20:14:56 -05:00
Thomas Harte
c07113ea95
Ensures no illegal accesses while testing MSX ROM type detection.
...
Specifically: the static analyser doesn't even correctly identify everything that is an MSX ROM yet, let alone then properly determine type.
2018-01-01 17:38:26 -05:00
Thomas Harte
bc2879c412
Corrects the MSX ROM unit test.
...
I.e. the test is correct now, for those SHAs I could find. The static analyser is still wrong just slightly less than half the time.
2018-01-01 17:35:13 -05:00
Thomas Harte
db25b4554b
Introduces failing tests of the MSX static analyser.
2018-01-01 16:38:26 -05:00
Thomas Harte
05b95ea2e0
Corrects Xcode tests.
2018-01-01 16:04:13 -05:00
Thomas Harte
6e1d69581c
Eliminates a variety of end-of-line spaces.
2017-11-07 22:54:22 -05:00
Thomas Harte
f95515ae81
Eliminates a large number of instance of end-of-line tabs.
2017-11-07 22:51:06 -05:00
Thomas Harte
064f1dfdbc
Removes usages of deprecated initialiser.
2017-10-05 18:10:47 -04:00
Thomas Harte
ff24e1de31
Corrects 6522 bridge per has-a-not-is-a template switch.
2017-09-04 21:56:21 -04:00
Thomas Harte
7af3de010e
Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
2017-08-23 22:25:31 -04:00
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
Thomas Harte
761afad118
Corrected timestamp return, and its testing by the 6502 timing tests.
2017-07-27 21:19:16 -04:00
Thomas Harte
37950143fc
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
Thomas Harte
9257a3f6d7
Added test for 16-bit arithmetic, and fixed implementation.
2017-07-26 19:04:52 -04:00
Thomas Harte
728143247d
Added a test for RLD and RRD. Which already passes.
2017-07-26 18:56:35 -04:00
Thomas Harte
6ec4e4e3d7
Merge branch 'master' into Memptr
2017-07-25 23:01:34 -04:00
Thomas Harte
37ccb9d3b6
Fixed 6502 timing tests.
2017-07-25 23:00:39 -04:00
Thomas Harte
3c254360ba
Completed fixture of the 6502 BCD test.
2017-07-25 22:55:45 -04:00
Thomas Harte
3ca51bedc6
Discovered legitimate uses of the jam opcode so reinstated it. Corrected illegitimate uses.
2017-07-25 22:48:44 -04:00
Thomas Harte
36076b7ea5
Eliminated final vestige of professed jam handling. This should make it clear which tests still think they can capture jams.
2017-07-25 22:38:26 -04:00
Thomas Harte
df4732be2e
Corrected test.
2017-07-24 22:33:49 -04:00
Thomas Harte
9435c1e12a
The 1540 is now a ClockReceiver.
2017-07-24 22:32:41 -04:00
Thomas Harte
2912d7055b
The 6532 is now a ClockReceiver.
2017-07-24 21:57:24 -04:00
Thomas Harte
13f7aa4063
The TIA is now a ClockReceiver.
2017-07-24 21:48:34 -04:00
Thomas Harte
b3ae920746
Converted the DPLL and disk controller classes to be ClockReceivers.
2017-07-24 21:04:47 -04:00
Thomas Harte
e6578defcd
It turns out that quite a few tests still rely on CSTestMachine6502JamOpcode. Though since it no longer works, that'll need to be fixed. In the meantime, fixed the test build process at least, as it's not really what this branch is meant to be invested in.
2017-07-23 22:22:50 -04:00
Thomas Harte
ace8e30818
Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
2017-07-23 22:21:39 -04:00
Thomas Harte
b0c2325adc
Corrected run call, and accepted that jam handling is gone forever.
2017-07-22 22:21:26 -04:00
Thomas Harte
4ea835e50b
Added test for EX (SP), rp, which passes.
2017-07-22 17:17:32 -04:00
Thomas Harte
6437c43147
Added CPI and CPD tests: at last two that pass without requiring implementation changes!
2017-07-22 12:38:18 -04:00
Thomas Harte
5928a24803
Transcribed missing tests as TODOs.
2017-07-22 11:44:17 -04:00
Thomas Harte
20a6bcc676
Added tests for the various LD (nn), rr instructions and corrected implementation to pass.
2017-07-22 11:39:13 -04:00
Thomas Harte
eaf313b0f6
Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.
2017-07-22 11:20:21 -04:00
Thomas Harte
d51b66c204
Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.
2017-07-21 23:01:35 -04:00
Thomas Harte
660f0e4c40
Added Objective-C through wiring and a Swift test class for Memptr modifications. So far with a single test, that fails.
2017-07-21 22:52:25 -04:00
Thomas Harte
7b5f93510b
Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.
2017-07-16 20:55:57 -04:00
Thomas Harte
8ddd686049
Removed redundant variable.
2017-07-16 19:04:03 -04:00
Thomas Harte
2fb0aea990
Updated the C1540 test vessel to the new world.
2017-07-16 17:00:39 -04:00
Thomas Harte
95a6b0f85c
Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
2017-06-22 21:09:26 -04:00
Thomas Harte
0e0ce379b4
Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
2017-06-21 20:38:08 -04:00
Thomas Harte
36e8a11505
Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
2017-06-21 20:32:08 -04:00
Thomas Harte
108da64562
Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
2017-06-20 22:25:00 -04:00
Thomas Harte
184b371649
Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
2017-06-20 21:48:50 -04:00
Thomas Harte
27ac342928
Corrected conditional call timing, and its test.
2017-06-20 20:57:23 -04:00
Thomas Harte
6752f165db
Added failing tests for both kinds of CALL.
2017-06-19 22:03:29 -04:00
Thomas Harte
e05076b258
Added tests for everything except CALL. All passing.
2017-06-19 22:00:04 -04:00
Thomas Harte
fadbfdf801
Added DJNZ test.
2017-06-19 21:31:56 -04:00
Thomas Harte
cb277b8d1e
Added JP and JR tests.
2017-06-19 21:27:23 -04:00
Thomas Harte
234f14dbbe
Tests were at fault; all passing now.
2017-06-19 21:14:40 -04:00
Thomas Harte
99ede3a9ef
BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).
2017-06-19 21:04:14 -04:00
Thomas Harte
378233f53d
Extended to BITs and SETs, accruing three new failures.
2017-06-19 21:01:30 -04:00
Thomas Harte
f903408980
Caught up on comments.
2017-06-19 20:53:22 -04:00
Thomas Harte
b684254908
Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
2017-06-19 20:33:34 -04:00
Thomas Harte
351d90ca55
Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.
2017-06-19 20:04:55 -04:00
Thomas Harte
23177df26a
Added various tests of the basic ALU ops.
2017-06-19 19:53:26 -04:00
Thomas Harte
ba15371948
Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
2017-06-19 19:47:00 -04:00
Thomas Harte
8d60734737
Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.
2017-06-19 19:17:54 -04:00
Thomas Harte
002098d496
The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.
2017-06-19 07:45:41 -04:00
Thomas Harte
85c5c4405a
Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
2017-06-19 07:30:01 -04:00
Thomas Harte
d668879ba6
Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
2017-06-18 22:03:13 -04:00
Thomas Harte
e1a2580b2a
Renamed BusOperation to MachineCycle::Operation.
2017-06-17 21:53:45 -04:00
Thomas Harte
b6f51474ff
Ensured that -description can handle the newly-captured bus actions.
2017-06-17 18:20:30 -04:00
Thomas Harte
0f18768091
Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.
2017-06-17 18:19:25 -04:00
Thomas Harte
50cd617bd9
Ensured test raises only the intentional failure exceptions.
2017-06-15 22:33:46 -04:00
Thomas Harte
838b818cd3
Finished transcribing first page of machine cycle documentation; several failures contained.
2017-06-15 22:19:49 -04:00
Thomas Harte
cf795562bf
Continued filling in tests, fleshing out what the test machine captures as a result.
2017-06-15 20:59:59 -04:00
Thomas Harte
ac37424878
Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.
2017-06-15 19:06:59 -04:00
Thomas Harte
aed2827e7b
Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
2017-06-12 22:22:00 -04:00
Thomas Harte
50be3a24fe
Sought to ensure that Mode 1 interrupts aren't happening early. Which they seem not to be.
2017-06-11 13:30:08 -04:00
Thomas Harte
2190f60a89
Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool.
2017-06-04 15:46:35 -04:00
Thomas Harte
0eebfdb4cc
Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.
2017-06-04 15:39:37 -04:00
Thomas Harte
7811374b0f
Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).
2017-06-04 15:07:07 -04:00
Thomas Harte
87095b0578
Undid consciously discard for bits 3 and 5 in the FUSE tests. Back to 100 failures.
2017-06-04 14:04:26 -04:00
Thomas Harte
b642d9f712
Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.
2017-06-03 21:54:42 -04:00
Thomas Harte
fd6623b5a5
Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
2017-06-03 21:22:16 -04:00
Thomas Harte
b3da16911f
Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.
2017-06-03 18:42:54 -04:00
Thomas Harte
e52892f75b
Added a test of interrupt mode 1.
2017-06-03 18:16:13 -04:00
Thomas Harte
8c41a0f0ed
Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.
2017-06-03 17:53:44 -04:00
Thomas Harte
3e9212aaff
Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
2017-06-03 17:41:45 -04:00
Thomas Harte
d14902700a
Minor syntax and wiring fixes.
2017-06-01 22:33:05 -04:00
Thomas Harte
c95c32a9fe
Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.
2017-06-01 22:31:04 -04:00
Thomas Harte
494ce073b5
Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging.
2017-05-31 19:58:57 -04:00
Thomas Harte
5ff73faf48
Ensured Zexall can pass.
2017-05-31 19:55:06 -04:00
Thomas Harte
2f7f11e2e5
Added diagnosis props.
2017-05-31 06:54:25 -04:00
Thomas Harte
5119997122
Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
2017-05-30 22:41:23 -04:00
Thomas Harte
244b5ba3c2
Added a proper termination condition for Zexall and, for now, a Mhz counter.
2017-05-30 18:32:38 -04:00
Thomas Harte
960de7bd7b
Marginally reduced test machine costs based on usage.
2017-05-30 11:59:07 -04:00
Thomas Harte
4d4695032c
Discovered that Zexall is just really slow. Disabled the address sanitiser, and started working towards a verifiable end.
2017-05-29 21:46:00 -04:00
Thomas Harte
6d22f6fcd5
Having decided the bus operation error on 10 is probably in the test cases, decided to allow myself to skip that one comparison. Back to zero failing cases, and with no more useful information to derive from the FUSE test set for the time being.
2017-05-29 17:17:17 -04:00
Thomas Harte
8bfaa487ce
Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit).
2017-05-29 17:13:24 -04:00
Thomas Harte
267b2add9a
Adjusted for where FUSE nominally places timestamps. Down to 92 failures.
2017-05-29 16:44:07 -04:00
Thomas Harte
d290e3d99e
Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!)
2017-05-29 16:35:00 -04:00
Thomas Harte
a6a4c5a936
Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures.
2017-05-29 15:57:27 -04:00
Thomas Harte
ed7b07c8b1
Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct.
2017-05-29 11:54:27 -04:00
Thomas Harte
d83dd17738
[DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed.
2017-05-29 11:40:56 -04:00
Thomas Harte
9ade0dcae3
One failure was just PUSH AF due to throwing away the 5 & 3 flags at the start. Switched to throwing them away at comparison.
2017-05-29 11:06:23 -04:00
Thomas Harte
a329d85697
Instituted memory value checks, flushing out seven new failures.
2017-05-29 11:01:45 -04:00
Thomas Harte
c322410783
Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation.
2017-05-29 10:52:54 -04:00
Thomas Harte
b67331e018
Fixing the OUT repetition group reduces the code to one failing test.
2017-05-29 10:48:53 -04:00
Thomas Harte
ad56a9215c
Implemented IN[I/D]x. 18 failures remaining.
2017-05-29 10:12:33 -04:00
Thomas Harte
c56a5344b9
Implemented CP[I/D]x.
2017-05-29 08:54:00 -04:00
Thomas Harte
409c82ce73
Implemented RLD and RRD. 34 failures remaining.
2017-05-28 16:46:27 -04:00
Thomas Harte
6e83b7d6df
Attempted to add a proper exit condition for Zexall.
2017-05-28 15:13:47 -04:00
Thomas Harte
5a4d448cc1
Corrected logical flags; now down to 68 failures, all of them on the ED page.
2017-05-28 15:09:58 -04:00
Thomas Harte
6b66c8f304
Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84.
2017-05-28 14:50:51 -04:00
Thomas Harte
035df316aa
FUSE seems to have inconsistent ideas about where b3 and b5 come from in more-complicated BIT instructions. So I'm not testing them for now. Within that reality, reduced to 102 failures.
2017-05-27 23:54:53 -04:00
Thomas Harte
c7cb47a1d8
Readded and then disabled my temporary one-test-only patch. Failures are currently at 237.
2017-05-27 21:10:25 -04:00
Thomas Harte
98423c6e41
Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues.
2017-05-27 16:19:15 -04:00
Thomas Harte
33c3fa21e3
Fixed (HL)/(In + d) CB page modify instructions. Reducing failures to 672.
2017-05-27 15:54:24 -04:00
Thomas Harte
9bc2b48d9b
Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures.
2017-05-26 23:23:33 -04:00
Thomas Harte
e4e71a1e5f
Switched back to descriptive failures, but put a cap on them.
2017-05-25 21:08:24 -04:00
Thomas Harte
fba5af280e
Shortened failure message, at least for now.
2017-05-25 21:05:47 -04:00
Thomas Harte
2cadc706e2
Now runs FUSE tests, albeit testing only a subset of the results. But enough to get started.
2017-05-25 21:00:33 -04:00
Thomas Harte
3c6f63abcc
Started towards running the FUSE tests. Just need to deal with the memory segments.
2017-05-25 19:12:59 -04:00
Thomas Harte
00cd7e7e9c
After hitting my head against the wall of trying to use [NS]Scanner as a parser some more, have given up and transcoded the two tests files to JSON.
2017-05-25 18:20:13 -04:00
Thomas Harte
055c860b43
Sealed off RegisterState as immutable, and started trying to parse the .expected file.
2017-05-23 22:32:36 -04:00
Thomas Harte
454c8628c3
Implemented an additional constructor for RegisterStates, pulling it out into file-level scope and implementing Equatable.
2017-05-23 22:05:33 -04:00
Thomas Harte
a23a6db4d6
Tidied up, creating a holder for RegisterState and giving it deserialisation logic. This makes sense because a register state will also need to be taken from the outputScanner, and from the machine.
2017-05-23 08:13:24 -04:00
Thomas Harte
6575091a78
Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly.
2017-05-22 21:50:34 -04:00
Thomas Harte
9e25d014d2
Made an attempt to log bus activity for comparison with FUSE results.
2017-05-22 19:49:38 -04:00
Thomas Harte
41d5dd8679
Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
2017-05-22 19:24:11 -04:00
Thomas Harte
22afa509ca
Got to a parsing and towards an attempt to run FUSE tests.
2017-05-22 19:14:46 -04:00
Thomas Harte
3fb3cc8269
Got explicit about encodings.
2017-05-21 22:53:06 -04:00
Thomas Harte
e3e461d7cb
Added a test class for running the FUSE tests. With nothing much in it.
2017-05-21 22:49:24 -04:00
Thomas Harte
c16fccb317
Fixed file names.
2017-05-21 22:43:07 -04:00
Thomas Harte
b9cffdf2bd
Imported the FUSE tests.
2017-05-21 22:42:20 -04:00
Thomas Harte
d910405648
Added enough infrastructure to be able to react to the two CP/M calls this cares about.
2017-05-19 21:53:39 -04:00
Thomas Harte
62b432c046
Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.
2017-05-19 21:20:28 -04:00
Thomas Harte
a3dafa9056
Abbreviated uses of enumerations.
2017-05-17 21:44:08 -04:00
Thomas Harte
64d6ee1be5
Adjusted slightly to adapt to latest Swift warnings.
2017-05-17 07:49:48 -04:00
Thomas Harte
1378ab7278
Ensured initial program counter and stack pointer are correct for Zexall, fixed the Z80 to use a compile-time polymorphic call for bus access.
2017-05-17 07:36:06 -04:00
Thomas Harte
87a021ec2d
Made further attempt to get as fas as having the Z80 attempt to do something.
2017-05-16 22:19:40 -04:00
Thomas Harte
189317b80c
Added enough of a Z80 test machine to bridge up into Swift.
2017-05-16 22:05:42 -04:00
Thomas Harte
4f0775cc7c
Imported the Zexall.com tester, as a first thing to throw at the Z80 to be.
2017-05-16 21:37:09 -04:00
Thomas Harte
df80c37adb
Renamed TestMachine to TestMachine6502 since there's going to be multiple of them.
2017-05-15 08:18:57 -04:00
Thomas Harte
0808e9b6fb
Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.
2017-05-14 22:08:15 -04:00
Thomas Harte
a6897ebde0
Added an attempt to distinguish the MegaBoy (now with proper capitalisation) and a test for it.
2017-03-13 20:43:12 -04:00
Thomas Harte
582da14a14
Added an enumerated type and detection of Pitfall 2.
2017-03-13 08:15:36 -04:00
Thomas Harte
8e147444d5
Added a readme, as is traditional for folders I'm excluding from Git.
2017-03-12 22:16:12 -04:00
Thomas Harte
2c07cce282
Had the wrong paging scheme listed for Robot Tank and Thwocker. Better to get this right before trying to come up with a test for the Activision stack scheme.
2017-03-12 21:03:10 -04:00
Thomas Harte
597bd97b01
Corrected two more table errors.
2017-03-12 15:46:25 -04:00
Thomas Harte
38de5300e5
Elevator Action seemingly uses a Super Chip.
2017-03-12 15:43:42 -04:00
Thomas Harte
146f3ea0f5
Fixed: Crystal Castles is 16kb.
2017-03-12 15:39:07 -04:00
Thomas Harte
78213f1e95
Fixed a couple more table entries, introduced per-size tests (plus a catch-all), to speed up the development/testing cycle.
2017-03-12 15:35:36 -04:00
Thomas Harte
de347ad7c8
Improved CBS RAM Plus and Super Chip detection exclusion, reducing error count to 15.
2017-03-12 14:03:17 -04:00
Thomas Harte
a4bba8a92e
Made a couple of lookup table fixes and corrected RAM region detection windows; failures now down to 19.
2017-03-11 23:18:30 -05:00
Thomas Harte
fcacfc2726
Tidied up spacing, slightly.
2017-03-11 23:01:42 -05:00
Thomas Harte
bab464e765
I'm far from confident, but this should reduce the deviations close to those that result from mistakes by the static analyser, rather than table errors.
2017-03-11 22:58:11 -05:00
Thomas Harte
2879763c34
Reduced to 84 failures through more accurate tabulation.
2017-03-11 21:52:52 -05:00
Thomas Harte
ea2ea30193
Fleshed entire table out with most common values. Exceptions now to fix.
2017-03-11 21:11:25 -05:00
Thomas Harte
608569cc48
Typed out all the 'A's that I am aware of. So about 5% done.
2017-03-11 20:58:38 -05:00
Thomas Harte
c7e973aab4
Extended test set a little, corrected current failures.
2017-03-11 20:51:25 -05:00
Thomas Harte
443d57bc32
Slimmed output and added first six tests. Acid Drop fails since I'm not yet declaring Atari 16k and Atari 32k.
2017-03-11 20:43:19 -05:00
Thomas Harte
57ec756f5b
Started speccing out a unit test for Atari ROM analysis.
2017-03-11 20:33:58 -05:00
Thomas Harte
d3257c345a
Tested against public ROMs and corrected. Also moved the deferred adjustment into a more canonical place.
2017-03-04 17:00:28 -05:00
Thomas Harte
e09b76bf32
Fixed 'same value, then immediate increment, then proper counting increments' behaviour and ensured it takes one cycle to commit a value. Adjusted tests to match.
2017-03-04 15:57:54 -05:00
Thomas Harte
dd17459687
Added my first failing test: delay is incorrect when resetting outside of the play area.
2017-02-12 20:42:49 -05:00
Thomas Harte
cd90118a0f
Added two, extraordinarily simple tests.
2017-02-12 20:32:53 -05:00
Thomas Harte
a568172758
Made steps towards proper CRC generation. Am currently comparing against Oric disk images, as — amongst other things — they include precomputed CRCs.
2016-12-28 18:29:37 -05:00
Thomas Harte
99993a1b24
Since it's about to become important that objective results match, added a couple of objective-result tests for the CRC generator.
2016-12-27 19:03:46 -05:00
Thomas Harte
d606bd7ce5
Added saturation test, fixed code as indicated.
2016-12-24 23:29:37 -05:00
Thomas Harte
09ff9d6a26
Introduced a couple more floating-point conversion tests, fixed errors uncovered.
2016-12-24 23:21:19 -05:00
Thomas Harte
e25195a718
Added a single test for Storage::Time, discovering that I had the wrong sign on float conversions.
2016-12-24 22:59:01 -05:00
Thomas Harte
7028f57336
Simplified a little further.
2016-12-22 18:13:10 -05:00
Thomas Harte
e4e0347638
Attempted to consolidate some of the repetition.
2016-12-21 22:17:00 -05:00
Thomas Harte
72ca06cf8d
Added some extra tests, performed some basic tidying. Probably should do more.
2016-12-21 19:54:19 -05:00
Thomas Harte
6a0c7f22ee
Added a few more tests. All passing.
2016-12-20 21:46:34 -05:00
Thomas Harte
03579f33f1
Fixed multi-coverage insertion, via an appropriate test.
2016-12-20 21:38:32 -05:00
Thomas Harte
7eca910cc5
Fixed insertion location finding logic, working on the relevant test.
2016-12-20 21:14:05 -05:00
Thomas Harte
c180340474
Added two more passing tests and one that crashes.
2016-12-20 19:25:58 -05:00
Thomas Harte
823ab9bc34
Completed initial non-trivial test, fixing revealed errors.
2016-12-20 19:15:36 -05:00
Thomas Harte
6bdde542c5
Edging towards functioning automatic tests, fixed right-period adjustment and slightly decreased searching cost while in the process of adding a test.
2016-12-20 07:52:14 -05:00
Thomas Harte
1df478d250
Removed dead header file.
2016-12-18 23:04:16 -05:00
Thomas Harte
e081f224b6
Implemented a very basic PCMTrack test, nevertheless revealing an oversight in PCMSegmentEventSource related to improperly counting to the index hole if the final bit is set. Took that as a message that I should comment and document the event source.
2016-12-18 22:53:24 -05:00
Thomas Harte
f9a5595dad
Added seeking tests, correcting such errors as uncovered.
2016-12-18 10:19:24 -05:00
Thomas Harte
3116a2cf4c
Realised I was actually testing PCMSegmentEventSource, not PCMSegment; implemented a spread of tests; hence fixed PCMSegmentEventSource.
2016-12-17 21:47:13 -05:00
Thomas Harte
254cc41fd6
Made an attempt to separate and isolate the stuff of creating flux events from a PCMSegment, eventually to factor that out of PCMTrack and make it available also to PCMPatchedTrack.
2016-12-17 21:13:57 -05:00
Thomas Harte
313db75303
Ensured the patchable track owns its underlying track.
2016-12-17 18:17:22 -05:00
Thomas Harte
3017062e89
Maybe TDD is the way to get over my activity block on this thing? Fixed the existing ArrayBuilder tests so that the tests target builds again, added an extremely trivial PCMTrack test, heading towards PCMPatchedTrack tests.
2016-12-17 17:05:49 -05:00
Thomas Harte
d17751787a
The remainder of this test isn't necessarily safe to perform if the array length isn't as expected. But in that case the test has already failed, so it's not worth worrying about a partial validation.
2016-12-03 16:06:15 -05:00
Thomas Harte
be60eaa120
Added a test for pointer continuity over a submit. Which fails.
2016-11-19 19:48:16 +08:00
Thomas Harte
274ec9efb8
Added a test for interceding submit.
2016-11-19 08:59:21 +08:00
Thomas Harte
22cb8ecd75
Started building some tests of the array builder.
2016-11-19 08:27:08 +08:00
Thomas Harte
dda0c8af30
Fixed tests.
2016-11-05 12:58:56 -04:00
Thomas Harte
70973eb850
Fixed accreditation of BCDTest.
2016-11-01 22:40:48 -04:00
Thomas Harte
23376257dc
Let's try this not as markup.
2016-11-01 22:36:07 -04:00
Thomas Harte
bddc540c0d
Partitioned and added text for AllSuiteA and Klaus Dormann's tests.
2016-11-01 22:35:15 -04:00
Thomas Harte
ca3e1c3204
Added an appropriate licence and credit for Wolfgang Lorenz's suite.
2016-11-01 22:26:12 -04:00
Thomas Harte
4b347b9993
Made a trivial XCTAssert unit test substitution.
2016-10-30 20:30:32 -04:00
Thomas Harte
534b3d085d
Improved test reporting, attempted to resolve timing errors just introduced (i.e. to differentiate break/continue where a cycle may or may not be spent).
2016-10-27 08:41:44 -04:00
Thomas Harte
f7d2e988b6
Mildly enhanced unit test, while I'm curious.
2016-10-11 22:22:53 -04:00
Thomas Harte
c097886d00
Installed hoglet's BCDTest as a formal part of the test suite; removed some redundant semicolons in the Wolfgang Lorenz tests while I was here.
2016-10-04 07:52:44 -04:00
Thomas Harte
fa7c64bb5d
Eventually reached an implementation of ADC that continues to satisfy all the formalised unit tests while also satisfying the manual BCDTest, that I need to find a way to formalise. I fixed the unit tests for Swift 3 while here, and attempted to do some unrelated NIB stuff with no real success.
2016-10-03 22:03:39 -04:00
Thomas Harte
7c65c69e0f
Migrated to Swift 3.
2016-09-15 22:12:12 -04:00
