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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-16 04:05:16 +00:00
Code Issues Projects Releases Wiki Activity
11,582 Commits 8 Branches 121 Tags 496 MiB
88bb16f261
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3374 Commits

Author SHA1 Message Date
Thomas Harte
88bb16f261 Install proper filter frequency. 2024-04-13 15:34:39 -04:00
Thomas Harte
c134c7bdc2 Fix: signal is 'flyback', not sync. 2024-04-10 21:53:38 -04:00
Thomas Harte
6c6cda3db5 Use clocking hints. 2024-04-09 22:22:03 -04:00
Thomas Harte
a29f246536 Move to more natural position of ownership. 2024-04-09 22:10:07 -04:00
Thomas Harte
d9d675a74f Fix scan status scale. 2024-04-09 21:56:42 -04:00
Thomas Harte
d62ea95889 Make some intimation towards audio. 2024-04-09 21:53:40 -04:00
Thomas Harte
e2e951ad0b Fix layout. 2024-04-09 21:49:35 -04:00
Thomas Harte
a5a653d684 Factor vsync state into IO reads. 2024-04-09 21:49:00 -04:00
Thomas Harte
6123350895 Improve state guesswork. 2024-04-09 21:24:08 -04:00
Thomas Harte
ec73c00c3b Silence the routine stuff of interrupt masks. 2024-04-09 20:57:57 -04:00
Thomas Harte
dd24f5f4f3 Don't latch video addresses until almost the last minute. 2024-04-09 20:56:10 -04:00
Thomas Harte
169298af42 Plumb through disk insertion. 
Surprisingly: some things now load.
 2024-04-08 21:15:40 -04:00
Thomas Harte
5e502df48b Forward motor and drive selection. 2024-04-07 22:29:00 -04:00
Thomas Harte
4f58664f97 Catch interrupt enables. 2024-04-07 22:08:12 -04:00
Thomas Harte
ffd298218c Tie off initial values; fix FIQ usage. 2024-04-07 21:58:16 -04:00
Thomas Harte
d2b077c573 Start wiring in a floppy controller. 2024-04-07 21:22:35 -04:00
Thomas Harte
547dc29a60 Remove done TODOs. 2024-04-07 15:53:42 -04:00
Thomas Harte
69aeca5c0e Aggregate mouse deltas where possible. 2024-04-06 21:24:21 -04:00
Thomas Harte
ed7cd4b277 Fix 8bpp output, all-modes cursor. 2024-04-06 20:58:44 -04:00
Thomas Harte
7bf831e1a6 Add missing 'override'. 2024-04-06 13:51:33 -04:00
Thomas Harte
0092cb8c36 Route enough to be able to mess around. 2024-04-06 13:44:05 -04:00
Thomas Harte
543b1c644a Wire mouse events to the relevant class. 2024-04-06 13:32:59 -04:00
Thomas Harte
cfaea7a90c Add cursor within 4bpp pixel area. 2024-04-05 22:43:10 -04:00
Thomas Harte
b821645644 Capture cursor palette, switch horizontal field. 2024-04-05 22:01:01 -04:00
Thomas Harte
2865190499 Resolve video addressing issues. 2024-04-05 21:56:31 -04:00
Thomas Harte
3f40e409c5 Reduce debugging heft. 2024-04-04 22:16:11 -04:00
Thomas Harte
002e235d90 Force RGB mode. 2024-04-04 22:02:47 -04:00
Thomas Harte
7d8a364658 Reimplement LDM and STM. 2024-04-04 21:59:18 -04:00
Thomas Harte
55369464ad Add a by-eye crop. A better answer will come. 2024-04-01 22:10:05 -04:00
Thomas Harte
609c117267 Switch to English RISC OS. 2024-04-01 21:44:42 -04:00
Thomas Harte
3b62a2fe7a Restrict video buffer to first 512kb. 2024-04-01 21:39:10 -04:00
Thomas Harte
0866caf934 Flaws remain, but acknowledge that pixel rate is double. 2024-04-01 10:48:20 -04:00
Thomas Harte
914b88d115 Fix non-debug build. 2024-03-31 19:17:55 -04:00
Thomas Harte
cc122a7a68 Add an SWI count, to aid in logging. 2024-03-31 18:18:26 -04:00
Thomas Harte
31979649c6 As it continues to swell, factor out the junk. 2024-03-31 18:15:48 -04:00
Thomas Harte
335d13d06d Mildly improve logging, define a few more ROMs. 2024-03-30 21:49:21 -04:00
Thomas Harte
ec785f3a8a Add URL as comment. 2024-03-30 20:54:17 -04:00
Thomas Harte
1f83a5425e Complete list of all currently-failing SWIs. 
... a lot of which are probably failing correctly, i.e. they're appropriately signalling.
 2024-03-30 20:48:47 -04:00
Thomas Harte
4882d6d0f2 Start adding SWI detail. 2024-03-30 15:16:48 -04:00
Thomas Harte
722743659b Add missing space. 2024-03-29 21:52:57 -04:00
Thomas Harte
6e64a79b52 Log failed SWIs. 2024-03-29 21:31:33 -04:00
Thomas Harte
8a6bf84cff Keyboard: log more, ignore unrecognised commands. 2024-03-29 20:54:07 -04:00
Thomas Harte
a0fdd8f4eb Resolve magic constant. 2024-03-28 22:15:27 -04:00
Thomas Harte
bda1783624 Make new guess at non-byte IOC reads. 2024-03-28 22:10:49 -04:00
Thomas Harte
2a14557478 Be more disciplined about errant accesses. 2024-03-28 21:31:07 -04:00
Thomas Harte
0ddbc67b1f Switch to default CMOS RAM obtained from RISC OS itself. 2024-03-28 21:23:49 -04:00
Thomas Harte
ffb5149890 Reinstate real CMOS RAM results. 2024-03-28 14:27:07 -04:00
Thomas Harte
4fcb85d132 Cleave off most remaining reasons for failure. 2024-03-28 10:32:27 -04:00
Thomas Harte
f175dcea58 Hack in some more potential debugging help. 2024-03-27 22:37:37 -04:00
Thomas Harte
f38bca37a2 Take another run at MEMC. 
I hadn't spotted that it is valid to map different logical pages to the same physical page with different protection levels.
 2024-03-27 10:44:40 -04:00