596 Commits

Author	SHA1	Message	Date
Thomas Harte	8c66e1d99d	Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data.	2017-06-06 17:53:23 -04:00
Thomas Harte	cc4cb45e9d	Implemented keyboard input and ensured that the signal generated is marked as composite, putting the colour-suppression ball into the CRT's court.	2017-06-06 09:25:18 -04:00
Thomas Harte	c485c460f7	Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.	2017-06-04 18:08:35 -04:00
Thomas Harte	b0a7c58287	Fixed project to point to the XIB I actually want to keep; fixed that XIB to have the correct contents.	2017-06-04 17:57:37 -04:00
Thomas Harte	d2637123c4	Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.	2017-06-04 17:55:19 -04:00
Thomas Harte	02b7c3d1b0	Added the necessary wiring to get into a ZX80/81-oriented part of the static analyser, which could in principle post a ZX80 target.	2017-06-04 17:04:06 -04:00
Thomas Harte	8c1769f157	Made a quick attempt at serialising from ZX80 .O to waves.	2017-06-04 16:59:26 -04:00
Thomas Harte	655809517c	Ensured that there is a subclass of file that is entrusted to load .O/.80 files, and that the code routes such files to it, noting that it should consider whether a ZX80 is required.	2017-06-04 16:37:03 -04:00
Thomas Harte	2190f60a89	Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool.	2017-06-04 15:46:35 -04:00
Thomas Harte	0eebfdb4cc	Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.	2017-06-04 15:39:37 -04:00
Thomas Harte	7811374b0f	Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).	2017-06-04 15:07:07 -04:00
Thomas Harte	87095b0578	Undid consciously discard for bits 3 and 5 in the FUSE tests. Back to 100 failures.	2017-06-04 14:04:26 -04:00
Thomas Harte	b642d9f712	Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.	2017-06-03 21:54:42 -04:00
Thomas Harte	fd6623b5a5	Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.	2017-06-03 21:22:16 -04:00
Thomas Harte	b304c3a4b9	Eliminated the 6502's reliance on the micro-op scheduler.	2017-06-03 20:30:07 -04:00
Thomas Harte	b3da16911f	Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.	2017-06-03 18:42:54 -04:00
Thomas Harte	e52892f75b	Added a test of interrupt mode 1.	2017-06-03 18:16:13 -04:00
Thomas Harte	8c41a0f0ed	Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.	2017-06-03 17:53:44 -04:00
Thomas Harte	3e9212aaff	Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.	2017-06-03 17:41:45 -04:00
Thomas Harte	d14902700a	Minor syntax and wiring fixes.	2017-06-01 22:33:05 -04:00
Thomas Harte	c95c32a9fe	Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.	2017-06-01 22:31:04 -04:00
Thomas Harte	494ce073b5	Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging.	2017-05-31 19:58:57 -04:00
Thomas Harte	5ff73faf48	Ensured Zexall can pass.	2017-05-31 19:55:06 -04:00
Thomas Harte	2f7f11e2e5	Added diagnosis props.	2017-05-31 06:54:25 -04:00
Thomas Harte	5119997122	Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.	2017-05-30 22:41:23 -04:00
Thomas Harte	7bddd294c9	Resolved an unpredictable conditional and temporarily disabled the Zexalltest as part of the default suite, since it takes so long to run.	2017-05-30 21:03:02 -04:00
Thomas Harte	244b5ba3c2	Added a proper termination condition for Zexall and, for now, a Mhz counter.	2017-05-30 18:32:38 -04:00
Thomas Harte	960de7bd7b	Marginally reduced test machine costs based on usage.	2017-05-30 11:59:07 -04:00
Thomas Harte	c6185baa99	Fixed R incrementation and attempted to make the status flags cheaper to write to.	2017-05-29 22:23:19 -04:00
Thomas Harte	4d4695032c	Discovered that Zexall is just really slow. Disabled the address sanitiser, and started working towards a verifiable end.	2017-05-29 21:46:00 -04:00
Thomas Harte	6d22f6fcd5	Having decided the bus operation error on 10 is probably in the test cases, decided to allow myself to skip that one comparison. Back to zero failing cases, and with no more useful information to derive from the FUSE test set for the time being.	2017-05-29 17:17:17 -04:00
Thomas Harte	8bfaa487ce	Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit).	2017-05-29 17:13:24 -04:00
Thomas Harte	267b2add9a	Adjusted for where FUSE nominally places timestamps. Down to 92 failures.	2017-05-29 16:44:07 -04:00
Thomas Harte	d290e3d99e	Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!)	2017-05-29 16:35:00 -04:00
Thomas Harte	a6a4c5a936	Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures.	2017-05-29 15:57:27 -04:00
Thomas Harte	ed7b07c8b1	Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct.	2017-05-29 11:54:27 -04:00
Thomas Harte	d83dd17738	[DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed.	2017-05-29 11:40:56 -04:00
Thomas Harte	9ade0dcae3	One failure was just PUSH AF due to throwing away the 5 & 3 flags at the start. Switched to throwing them away at comparison.	2017-05-29 11:06:23 -04:00
Thomas Harte	a329d85697	Instituted memory value checks, flushing out seven new failures.	2017-05-29 11:01:45 -04:00
Thomas Harte	c322410783	Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation.	2017-05-29 10:52:54 -04:00
Thomas Harte	b67331e018	Fixing the OUT repetition group reduces the code to one failing test.	2017-05-29 10:48:53 -04:00
Thomas Harte	ad56a9215c	Implemented IN[I/D]x. 18 failures remaining.	2017-05-29 10:12:33 -04:00
Thomas Harte	c56a5344b9	Implemented CP[I/D]x.	2017-05-29 08:54:00 -04:00
Thomas Harte	409c82ce73	Implemented RLD and RRD. 34 failures remaining.	2017-05-28 16:46:27 -04:00
Thomas Harte	6e83b7d6df	Attempted to add a proper exit condition for Zexall.	2017-05-28 15:13:47 -04:00
Thomas Harte	5a4d448cc1	Corrected logical flags; now down to 68 failures, all of them on the ED page.	2017-05-28 15:09:58 -04:00
Thomas Harte	6b66c8f304	Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84.	2017-05-28 14:50:51 -04:00
Thomas Harte	035df316aa	FUSE seems to have inconsistent ideas about where b3 and b5 come from in more-complicated BIT instructions. So I'm not testing them for now. Within that reality, reduced to 102 failures.	2017-05-27 23:54:53 -04:00
Thomas Harte	c7cb47a1d8	Readded and then disabled my temporary one-test-only patch. Failures are currently at 237.	2017-05-27 21:10:25 -04:00
Thomas Harte	98423c6e41	Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues.	2017-05-27 16:19:15 -04:00