Thomas Harte
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b3ae920746
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Converted the DPLL and disk controller classes to be ClockReceivers.
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2017-07-24 21:04:47 -04:00 |
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Thomas Harte
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e5188a60dc
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Settled on the new average-of-length approach to a PLL window sizing, eliminating the old errors-of-phase approach. Since it anchors automatically to the original target clocks per bit, killed the explicit mention of a tolerance.
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2017-07-16 19:03:50 -04:00 |
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Thomas Harte
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51177e4e1f
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Attempted a different implementation of the PLL, that responds to changes only once.
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2017-07-16 16:49:04 -04:00 |
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Thomas Harte
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4489f120f9
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Eliminated foolish double indirection on phase history.
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2017-07-15 22:40:38 -04:00 |
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Thomas Harte
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e01f3f06c8
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Completed curly bracket movement.
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2017-03-26 14:34:47 -04:00 |
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Thomas Harte
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0dc2aa6454
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Commuted all of 'Storage' other than 'Tape' to postfix underscores.
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2016-12-03 11:59:28 -05:00 |
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Thomas Harte
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015cea494d
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Switched to a much-more straightforward PLL. I think I'm just fiddling now rather than moving forwards. Probably time to move on?
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2016-07-28 11:32:14 -04:00 |
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Thomas Harte
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481475a0f4
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Switched to a full-on linear regression. Which causes the current tests to pass.
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2016-07-14 19:42:01 -04:00 |
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Thomas Harte
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d1fe07f14d
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Added test of perfect DPLL input timing.
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2016-07-12 21:42:23 -04:00 |
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Thomas Harte
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94db45456e
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Started sketching out the basic form here, albeit that it doesn't yet do _the only thing it advertises itself as useful for_.
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2016-07-12 20:23:56 -04:00 |
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Thomas Harte
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75d95c0bc0
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Sketched out an interface for a digial PLL. Not persuaded yet. Baby steps.
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2016-07-11 22:12:58 -04:00 |
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