Thomas Harte
8dd7c6ef23
Eliminates 'reversed_c' as I no longer believe low-resolution colour numbers are reversed.
...
Also gets explicit about phase.
2018-05-29 22:30:45 -04:00
Thomas Harte
a26ab7086d
Merge pull request #456 from TomHarte/TristateSleeper
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Commutes `Sleeper` to `ClockingHint::Source`
2018-05-28 18:25:21 -04:00
Thomas Harte
b2464598d0
Forces the Apple II bus handler call inline.
2018-05-28 18:21:01 -04:00
Thomas Harte
6812a001d8
Teaches the Oric to apply a lighter Disk II touch when possible.
2018-05-28 18:20:43 -04:00
Thomas Harte
6c16754a6b
Strips further improper constexpr
s.
2018-05-28 17:48:55 -04:00
Thomas Harte
75f9e3caeb
Resolves incorrect bracketing.
2018-05-28 17:48:35 -04:00
Thomas Harte
ad5afe21ee
Removes constexpr
from things which are not const. Duh.
2018-05-28 17:28:57 -04:00
Thomas Harte
8a566cc1dd
Experimentally goes to town on constexpr
.
2018-05-28 17:20:11 -04:00
Thomas Harte
928aab13dc
Introduces more granular clocking announcements to the Disk II.
...
As well as making it accept the clock rate it'll actually receive, to supply to the drives, so that they spin at the proper speed.
2018-05-28 17:19:29 -04:00
Thomas Harte
f3fe711542
Attempts to reduce FDC costs.
2018-05-27 23:55:04 -04:00
Thomas Harte
db8d8d8404
Commutes Sleeper
to ClockingHint::Source
, making state more granular.
2018-05-27 23:17:06 -04:00
Thomas Harte
6220ccb5d3
Merge pull request #455 from TomHarte/HumptyDumpty
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Relaxes .p validation even further
2018-05-27 17:01:07 -04:00
Thomas Harte
20843305dd
Removes unused calculation of vars
.
2018-05-27 13:31:30 -04:00
Thomas Harte
8f6c0f6a8d
Eliminates vars
test.
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At least Humpty Dumpty is a working .p that doesn't satisfy the test.
2018-05-26 19:05:35 -04:00
Thomas Harte
ede2df7e70
Merge pull request #452 from TomHarte/NIBWriting
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Adds write support for NIBs
2018-05-25 18:40:35 -04:00
Thomas Harte
d45231c1a8
Introduces an additional validation test.
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Thereby satisfying the TODO.
2018-05-25 18:40:15 -04:00
Thomas Harte
772812b35f
Corrects improper textual reference to interface names.
2018-05-25 18:31:20 -04:00
Thomas Harte
f443fd44b5
Introduces support for writing NIBs.
2018-05-25 18:30:55 -04:00
Thomas Harte
79c60b8984
Adds necessary import for memcpy
.
2018-05-24 21:58:50 -04:00
Thomas Harte
2dc2c2ce79
Merge pull request #449 from TomHarte/WOZWriting
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Implements write support for WOZ files
2018-05-24 21:48:28 -04:00
Thomas Harte
523ca3264b
Implements write support for WOZ files.
2018-05-24 21:44:31 -04:00
Thomas Harte
4036c60b45
Merge branch 'master' into WOZWriting
2018-05-24 19:01:04 -04:00
Thomas Harte
7d652e53e2
Merge pull request #450 from TomHarte/OricMicrodisc
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Corrects meaning of the Microdisc's paging control.
2018-05-24 18:58:07 -04:00
Thomas Harte
7c3dd55e5c
Corrects typo and improves exposition.
2018-05-24 18:57:35 -04:00
Thomas Harte
1b43381be0
Corrects meaning of the Microdisc's paging control.
2018-05-24 18:53:02 -04:00
Thomas Harte
8f78e5039e
Factors out track seeking.
2018-05-24 18:45:00 -04:00
Thomas Harte
57ee6d4e41
Merge branch 'master' into WOZWriting
2018-05-23 22:32:30 -04:00
Thomas Harte
2868b1eca7
Adds missing import for memcpy
.
2018-05-23 22:31:35 -04:00
Thomas Harte
a4d7703efd
Adds missing #include.
2018-05-23 22:28:00 -04:00
Thomas Harte
ca4bc92c33
Adds WOZ CRC checking.
2018-05-23 22:22:17 -04:00
Thomas Harte
853261364e
Generalised CRC generation and created specific subclasses for the CCITT CRC16 and CRC32.
2018-05-23 22:21:57 -04:00
Thomas Harte
d3c5e4267f
Merge pull request #447 from TomHarte/DiskIIWriting
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Substantially improves Disk II emulation, including write support
2018-05-22 21:54:16 -04:00
Thomas Harte
086b801c29
Mildly rearranges to avoid unnecessary call.
2018-05-22 21:50:07 -04:00
Thomas Harte
f9c25372c2
Ensures cards get messaged regardless of memory area.
2018-05-22 21:49:34 -04:00
Thomas Harte
ea92363e6c
Attempts to get the Apple II to honour the AppleII::Card select constraints appropriately.
2018-05-22 20:34:59 -04:00
Thomas Harte
015f692bd3
The Disk II card now commutes Disk II sleep activity to select constraints.
2018-05-22 19:51:39 -04:00
Thomas Harte
80d34f5511
Specs out a new AppleII::Card
interface.
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Doesn't yet fully implement it on the Apple II side though.
2018-05-21 20:54:53 -04:00
Thomas Harte
e482929da8
Enhances the Disk II's ability to sleep.
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Also enables Disk II sleep observation in the Oric.
2018-05-19 23:15:28 -04:00
Thomas Harte
4952657b31
Factors out physical to logical sector conversion.
2018-05-19 22:59:59 -04:00
Thomas Harte
46fae1a761
Corrected: now maps in the proper direction.
2018-05-19 22:50:33 -04:00
Thomas Harte
a09fb01d71
Makes an attempt at write support for Apple DSK files.
2018-05-19 22:30:52 -04:00
Thomas Harte
7cee3b7449
Resolves potential overflow / sign corruption.
2018-05-19 22:28:29 -04:00
Thomas Harte
8263c48a1d
Added a guarantee that the TrackSerialiser won't modify tracks it receives.
2018-05-18 23:03:28 -04:00
Thomas Harte
ed06533e60
Implements write support out of the Disk II.
2018-05-18 22:07:58 -04:00
Thomas Harte
7b7beb13a3
Eliminates the fiction of setting and getting registers.
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The Disk II seems lower level than that; it will read the data bus whenever it likes, it is the programmer's responsibility to keep up with that. It also reserves the right not to load the bus regardless of whether it receives a read or write access.
2018-05-17 21:39:11 -04:00
Thomas Harte
c46007332a
Switches to returning the shift register contents on every even read.
2018-05-17 20:18:34 -04:00
Thomas Harte
908d3b0ee5
Slightly wrong as to the details, but gets the controller trying to output.
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At an initial look, I think the shift register should end up on the data bus for all odd accesses. Need to investigate more thoroughly.
2018-05-16 22:37:22 -04:00
Thomas Harte
8a031b1137
Eliminates 'data' register as it doesn't exist; rejigs state machine command set.
2018-05-16 22:09:59 -04:00
Thomas Harte
1aba9f807e
Ensures proper upward propagation of sleeping from first start.
2018-05-16 22:07:54 -04:00
Thomas Harte
4c49963988
Switches to proper handling of the motor control and write protection.
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Per Understanding the Apple II the drive looks write protected while phase 1 is enabled.
2018-05-16 21:44:09 -04:00