Thomas Harte
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91223b9ec8
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Sets default level to high.
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2019-10-21 20:18:33 -04:00 |
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Thomas Harte
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83f5f0e2ad
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Begins trying to receive ACIA data.
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2019-10-21 20:10:19 -04:00 |
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Thomas Harte
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cf37e9f5de
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Remove source control markers.
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2019-10-20 23:40:51 -04:00 |
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Thomas Harte
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e4f7ead894
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Merge branch 'AtariST' of github.com:TomHarte/CLK into AtariST
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2019-10-20 23:40:01 -04:00 |
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Thomas Harte
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4134463094
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The ACIA now receives bits.
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2019-10-20 23:34:30 -04:00 |
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Thomas Harte
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83d73fb088
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The keyboard now responds to a reset on its serial line.
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2019-10-20 23:13:44 -04:00 |
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Thomas Harte
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cf07982a9b
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Ensures good serial line and ACIA behaviour.
Next stop: having the intelligent keyboard react.
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2019-10-20 22:10:05 -04:00 |
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Thomas Harte
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2e86dada1d
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Ensures updates even when the event queue is empty.
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2019-10-20 20:38:56 -04:00 |
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Thomas Harte
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696af5c3a6
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Starts to transfer serial line decoding logic into the line itself.
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2019-10-20 20:38:56 -04:00 |
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Thomas Harte
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f08b38d0ae
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Silences, temporarily.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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9a8352282d
|
Mostly but not quite fixes serial work.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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3d03cce6b1
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Starts working on the GPIP functionality block.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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34075a7674
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Attempts to tie an intelligent keyboard to the other end of its serial line.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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f79c87659f
|
Corrects documentation error.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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c10b64e1c0
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Adds a received_data_ register, that presently can never fill.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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5d5fe52144
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Corrects transmission logic — exactly hitting write_data_time_remaining now works properly.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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d461331fd2
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Ensures remaining_delays_ is set properly after [reset/flush]_writing.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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ff62eb6dce
|
The ACIA actually has two clocks, though on an ST they're both 500,000 Hz.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
|
374439693e
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Ensures serial lines know their writer's clock rate.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
|
c4ef33b23f
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JustInTimeActors can now specify a clock divider.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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a7ed357569
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Attempts to implement transmission interrupts and ClockingHint::Source.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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4e5b440145
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Attempts mostly to implement 6850 output.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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2bd7be13b5
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Decodes the 6850 control register, and starts working on standardised serial ports.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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4b09d7c41d
|
Nudges 6850 towards coherence.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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b0f5f7bd37
|
Attempts to start producing actual video.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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4ead905c3c
|
Adds an empty shell for the ACIA.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
|
127bb043e7
|
Adds enough logic to advance to an ACIA access error.
|
2019-10-20 20:38:55 -04:00 |
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Thomas Harte
|
2cf52fb89c
|
Makes an unsuccessful first attempt at some timer functionality.
|
2019-10-20 20:38:54 -04:00 |
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Thomas Harte
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6e1b606adf
|
Adds a target for MFP read/write operations.
Completely without any implementation, so far.
|
2019-10-20 20:38:54 -04:00 |
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Thomas Harte
|
e095a622d3
|
Ensures updates even when the event queue is empty.
|
2019-10-17 23:59:43 -04:00 |
|
Thomas Harte
|
9ab49065cd
|
Starts to transfer serial line decoding logic into the line itself.
|
2019-10-17 23:34:39 -04:00 |
|
Thomas Harte
|
ab50f17d87
|
Silences, temporarily.
|
2019-10-16 23:34:49 -04:00 |
|
Thomas Harte
|
f5a2e180f9
|
Mostly but not quite fixes serial work.
|
2019-10-16 23:34:37 -04:00 |
|
Thomas Harte
|
f2e1584275
|
Starts working on the GPIP functionality block.
|
2019-10-16 23:21:25 -04:00 |
|
Thomas Harte
|
0fd8813ddb
|
Attempts to tie an intelligent keyboard to the other end of its serial line.
|
2019-10-16 23:21:14 -04:00 |
|
Thomas Harte
|
b69180ba01
|
Corrects documentation error.
|
2019-10-16 23:19:42 -04:00 |
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Thomas Harte
|
c352d8ae8c
|
Adds a received_data_ register, that presently can never fill.
|
2019-10-13 23:04:57 -04:00 |
|
Thomas Harte
|
530e831064
|
Corrects transmission logic — exactly hitting write_data_time_remaining now works properly.
|
2019-10-13 21:40:46 -04:00 |
|
Thomas Harte
|
3b165a78f2
|
Ensures remaining_delays_ is set properly after [reset/flush]_writing.
|
2019-10-13 21:39:25 -04:00 |
|
Thomas Harte
|
8d87e9eb1c
|
The ACIA actually has two clocks, though on an ST they're both 500,000 Hz.
|
2019-10-13 21:32:34 -04:00 |
|
Thomas Harte
|
f86dc082bb
|
Ensures serial lines know their writer's clock rate.
|
2019-10-13 20:41:08 -04:00 |
|
Thomas Harte
|
d7982aa84e
|
JustInTimeActors can now specify a clock divider.
|
2019-10-13 18:19:39 -04:00 |
|
Thomas Harte
|
516d78f5a8
|
Attempts to implement transmission interrupts and ClockingHint::Source.
|
2019-10-12 23:46:57 -04:00 |
|
Thomas Harte
|
8b50a7d6e3
|
Attempts mostly to implement 6850 output.
|
2019-10-12 23:14:29 -04:00 |
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Thomas Harte
|
4bf81d3b90
|
Decodes the 6850 control register, and starts working on standardised serial ports.
|
2019-10-12 18:19:55 -04:00 |
|
Thomas Harte
|
cd75978e4e
|
Nudges 6850 towards coherence.
|
2019-10-12 00:04:02 -04:00 |
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Thomas Harte
|
c5ebf75351
|
Attempts to start producing actual video.
|
2019-10-10 22:46:58 -04:00 |
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Thomas Harte
|
d7ce2c26e8
|
Adds an empty shell for the ACIA.
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2019-10-10 20:54:29 -04:00 |
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Thomas Harte
|
f88e1b1373
|
Adds enough logic to advance to an ACIA access error.
|
2019-10-09 23:01:11 -04:00 |
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Thomas Harte
|
1de1818ebb
|
Makes an unsuccessful first attempt at some timer functionality.
|
2019-10-07 22:44:35 -04:00 |
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