Thomas Harte
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9257a3f6d7
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Added test for 16-bit arithmetic, and fixed implementation.
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2017-07-26 19:04:52 -04:00 |
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Thomas Harte
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728143247d
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Added a test for RLD and RRD. Which already passes.
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2017-07-26 18:56:35 -04:00 |
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Thomas Harte
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6ec4e4e3d7
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Merge branch 'master' into Memptr
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2017-07-25 23:01:34 -04:00 |
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Thomas Harte
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37ccb9d3b6
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Fixed 6502 timing tests.
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2017-07-25 23:00:39 -04:00 |
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Thomas Harte
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3c254360ba
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Completed fixture of the 6502 BCD test.
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2017-07-25 22:55:45 -04:00 |
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Thomas Harte
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3ca51bedc6
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Discovered legitimate uses of the jam opcode so reinstated it. Corrected illegitimate uses.
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2017-07-25 22:48:44 -04:00 |
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Thomas Harte
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36076b7ea5
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Eliminated final vestige of professed jam handling. This should make it clear which tests still think they can capture jams.
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2017-07-25 22:38:26 -04:00 |
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Thomas Harte
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279c369a1f
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Switched to Cycles as the result from the 6502 perform_bus_operation, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.
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2017-07-25 22:21:09 -04:00 |
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Thomas Harte
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75d67ee770
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Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
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2017-07-25 20:20:55 -04:00 |
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Thomas Harte
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df4732be2e
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Corrected test.
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2017-07-24 22:33:49 -04:00 |
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Thomas Harte
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9435c1e12a
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The 1540 is now a ClockReceiver.
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2017-07-24 22:32:41 -04:00 |
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Thomas Harte
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2912d7055b
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The 6532 is now a ClockReceiver.
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2017-07-24 21:57:24 -04:00 |
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Thomas Harte
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13f7aa4063
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The TIA is now a ClockReceiver.
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2017-07-24 21:48:34 -04:00 |
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Thomas Harte
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b3ae920746
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Converted the DPLL and disk controller classes to be ClockReceivers.
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2017-07-24 21:04:47 -04:00 |
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Thomas Harte
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e6578defcd
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It turns out that quite a few tests still rely on CSTestMachine6502JamOpcode. Though since it no longer works, that'll need to be fixed. In the meantime, fixed the test build process at least, as it's not really what this branch is meant to be invested in.
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2017-07-23 22:22:50 -04:00 |
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Thomas Harte
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ace8e30818
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Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
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2017-07-23 22:21:39 -04:00 |
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Thomas Harte
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b0c2325adc
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Corrected run call, and accepted that jam handling is gone forever.
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2017-07-22 22:21:26 -04:00 |
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Thomas Harte
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2ff157cf7a
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Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that.
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2017-07-22 22:17:29 -04:00 |
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Thomas Harte
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1ba3f262a2
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Sketched out a template for clock-receiving components to allow them to be implemented in terms of either half or whole cycles.
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2017-07-22 21:46:50 -04:00 |
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Thomas Harte
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4ea835e50b
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Added test for EX (SP), rp, which passes.
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2017-07-22 17:17:32 -04:00 |
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Thomas Harte
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5fddbec132
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Merge branch 'master' into Memptr
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2017-07-22 17:06:22 -04:00 |
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Thomas Harte
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6633537fb8
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Discovering that there is such a thing as P81 — a ZX81 file without the name omitted — added support for it. Extended FileHolder while I was here to retain the file name and be able to supply its extension, as my quick-fix test-the-last-character approach to o/p/80/81 discrimination stops working with p81 thrown into the mix and this feels like the correct factoring.
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2017-07-22 16:02:25 -04:00 |
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Thomas Harte
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6437c43147
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Added CPI and CPD tests: at last two that pass without requiring implementation changes!
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2017-07-22 12:38:18 -04:00 |
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Thomas Harte
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5928a24803
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Transcribed missing tests as TODOs.
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2017-07-22 11:44:17 -04:00 |
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Thomas Harte
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20a6bcc676
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Added tests for the various LD (nn), rr instructions and corrected implementation to pass.
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2017-07-22 11:39:13 -04:00 |
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Thomas Harte
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eaf313b0f6
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Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.
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2017-07-22 11:20:21 -04:00 |
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Thomas Harte
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d51b66c204
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Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.
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2017-07-21 23:01:35 -04:00 |
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Thomas Harte
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660f0e4c40
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Added Objective-C through wiring and a Swift test class for Memptr modifications. So far with a single test, that fails.
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2017-07-21 22:52:25 -04:00 |
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Thomas Harte
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2b5d0877a8
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Adjusted parameter name to match documentation. I think it's a carry-over from before I was passing the whole event along.
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2017-07-21 21:27:50 -04:00 |
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Thomas Harte
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2a7fc86b15
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Enabled stricter warnings.
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2017-07-21 20:44:35 -04:00 |
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Thomas Harte
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8f72fc4a44
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Factored out from the UEF implementation the concept of being a tape that has a queue of pending pulses and manages that queue.
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2017-07-16 22:04:40 -04:00 |
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Thomas Harte
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238348c885
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Performed the initial wiring to announce that this application supports TZX files and to route them to the ZX80/81 static analyser. The TZX class itself does not yet do much beyond basic validation. I think it'll be easiest if it follows in UEF's footsteps in queuing up pulses ahead of time, so some factoring out is now required.
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2017-07-16 21:33:11 -04:00 |
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Thomas Harte
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7b5f93510b
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Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.
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2017-07-16 20:55:57 -04:00 |
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Thomas Harte
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8ddd686049
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Removed redundant variable.
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2017-07-16 19:04:03 -04:00 |
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Thomas Harte
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2fb0aea990
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Updated the C1540 test vessel to the new world.
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2017-07-16 17:00:39 -04:00 |
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Thomas Harte
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279f4760d7
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Eliminated buffer_size_ as something explicitly stored, and reduced size of delegate call out.
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2017-07-16 15:01:39 -04:00 |
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Thomas Harte
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368bff1a82
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Added a shell class that will one day be able to parse CSW files, plus the logic and metadata to instantiate it when a CSW presents itself.
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2017-07-10 21:43:58 -04:00 |
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Thomas Harte
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3e5c209039
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Added basic Typer support for the ZX80 and '81.
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2017-07-09 22:00:34 -04:00 |
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Thomas Harte
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54efcb7e2f
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Made a game attempt at automatic motor control and ensured setting is initialised correctly from the user defaults.
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2017-07-08 19:31:20 -04:00 |
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Thomas Harte
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e2575d6de4
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Routed tape motor selections through to the C++ side of the world, and ensured that manual tape playback works properly.
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2017-07-08 19:21:12 -04:00 |
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Thomas Harte
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23e989e170
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This will likely do for the Swift/XIB side of things: the play/pause button is enabled or disabled as per the user's choice of automatic tape control, and toggles function when pressed. It communicates activity down to the Objective-C[++] layer, giving it a route through to the actual machine.
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2017-07-08 19:12:06 -04:00 |
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Thomas Harte
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28412150e6
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Added controls for controlling the tape motor of the ZX80/81, assuming I can find an automatic option.
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2017-07-08 17:59:33 -04:00 |
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Thomas Harte
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cb105fdeb4
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Took a first stab at high-res support.
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2017-06-22 22:48:17 -04:00 |
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Thomas Harte
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aec4fd066b
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I think I've definitively decided against this model of timing.
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2017-06-22 21:32:14 -04:00 |
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Thomas Harte
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95a6b0f85c
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Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
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2017-06-22 21:09:26 -04:00 |
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Thomas Harte
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644ef13acd
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Connected up the fast-tape GUI option for the ZX80 and '81.
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2017-06-22 20:20:31 -04:00 |
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Thomas Harte
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0e0ce379b4
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Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
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2017-06-21 20:38:08 -04:00 |
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Thomas Harte
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36e8a11505
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Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
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2017-06-21 20:32:08 -04:00 |
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Thomas Harte
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108da64562
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Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
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2017-06-20 22:25:00 -04:00 |
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Thomas Harte
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184b371649
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Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
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2017-06-20 21:48:50 -04:00 |
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