Thomas Harte
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9ade0dcae3
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One failure was just PUSH AF due to throwing away the 5 & 3 flags at the start. Switched to throwing them away at comparison.
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2017-05-29 11:06:23 -04:00 |
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Thomas Harte
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a329d85697
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Instituted memory value checks, flushing out seven new failures.
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2017-05-29 11:01:45 -04:00 |
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Thomas Harte
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c322410783
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Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation.
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2017-05-29 10:52:54 -04:00 |
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Thomas Harte
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b67331e018
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Fixing the OUT repetition group reduces the code to one failing test.
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2017-05-29 10:48:53 -04:00 |
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Thomas Harte
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ad56a9215c
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Implemented IN[I/D]x. 18 failures remaining.
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2017-05-29 10:12:33 -04:00 |
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Thomas Harte
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c56a5344b9
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Implemented CP[I/D]x.
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2017-05-29 08:54:00 -04:00 |
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Thomas Harte
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409c82ce73
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Implemented RLD and RRD. 34 failures remaining.
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2017-05-28 16:46:27 -04:00 |
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Thomas Harte
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6e83b7d6df
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Attempted to add a proper exit condition for Zexall.
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2017-05-28 15:13:47 -04:00 |
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Thomas Harte
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5a4d448cc1
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Corrected logical flags; now down to 68 failures, all of them on the ED page.
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2017-05-28 15:09:58 -04:00 |
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Thomas Harte
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6b66c8f304
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Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84.
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2017-05-28 14:50:51 -04:00 |
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Thomas Harte
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035df316aa
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FUSE seems to have inconsistent ideas about where b3 and b5 come from in more-complicated BIT instructions. So I'm not testing them for now. Within that reality, reduced to 102 failures.
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2017-05-27 23:54:53 -04:00 |
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Thomas Harte
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c7cb47a1d8
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Readded and then disabled my temporary one-test-only patch. Failures are currently at 237.
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2017-05-27 21:10:25 -04:00 |
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Thomas Harte
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98423c6e41
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Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues.
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2017-05-27 16:19:15 -04:00 |
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Thomas Harte
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33c3fa21e3
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Fixed (HL)/(In + d) CB page modify instructions. Reducing failures to 672.
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2017-05-27 15:54:24 -04:00 |
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Thomas Harte
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9bc2b48d9b
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Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures.
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2017-05-26 23:23:33 -04:00 |
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Thomas Harte
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e4e71a1e5f
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Switched back to descriptive failures, but put a cap on them.
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2017-05-25 21:08:24 -04:00 |
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Thomas Harte
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fba5af280e
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Shortened failure message, at least for now.
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2017-05-25 21:05:47 -04:00 |
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Thomas Harte
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2cadc706e2
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Now runs FUSE tests, albeit testing only a subset of the results. But enough to get started.
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2017-05-25 21:00:33 -04:00 |
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Thomas Harte
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3c6f63abcc
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Started towards running the FUSE tests. Just need to deal with the memory segments.
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2017-05-25 19:12:59 -04:00 |
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Thomas Harte
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00cd7e7e9c
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After hitting my head against the wall of trying to use [NS]Scanner as a parser some more, have given up and transcoded the two tests files to JSON.
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2017-05-25 18:20:13 -04:00 |
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Thomas Harte
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055c860b43
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Sealed off RegisterState as immutable, and started trying to parse the .expected file.
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2017-05-23 22:32:36 -04:00 |
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Thomas Harte
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454c8628c3
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Implemented an additional constructor for RegisterStates, pulling it out into file-level scope and implementing Equatable.
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2017-05-23 22:05:33 -04:00 |
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Thomas Harte
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a23a6db4d6
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Tidied up, creating a holder for RegisterState and giving it deserialisation logic. This makes sense because a register state will also need to be taken from the outputScanner, and from the machine.
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2017-05-23 08:13:24 -04:00 |
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Thomas Harte
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6575091a78
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Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly.
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2017-05-22 21:50:34 -04:00 |
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Thomas Harte
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9e25d014d2
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Made an attempt to log bus activity for comparison with FUSE results.
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2017-05-22 19:49:38 -04:00 |
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Thomas Harte
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41d5dd8679
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Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
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2017-05-22 19:24:11 -04:00 |
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Thomas Harte
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22afa509ca
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Got to a parsing and towards an attempt to run FUSE tests.
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2017-05-22 19:14:46 -04:00 |
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Thomas Harte
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3fb3cc8269
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Got explicit about encodings.
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2017-05-21 22:53:06 -04:00 |
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Thomas Harte
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e3e461d7cb
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Added a test class for running the FUSE tests. With nothing much in it.
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2017-05-21 22:49:24 -04:00 |
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Thomas Harte
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c16fccb317
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Fixed file names.
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2017-05-21 22:43:07 -04:00 |
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Thomas Harte
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b9cffdf2bd
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Imported the FUSE tests.
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2017-05-21 22:42:20 -04:00 |
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Thomas Harte
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01a064dd63
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Added an empty ED page.
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2017-05-20 17:29:30 -04:00 |
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Thomas Harte
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d910405648
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Added enough infrastructure to be able to react to the two CP/M calls this cares about.
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2017-05-19 21:53:39 -04:00 |
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Thomas Harte
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62b432c046
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Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.
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2017-05-19 21:20:28 -04:00 |
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Thomas Harte
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11d05fb3b8
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Expanded a little on operations, added an implementation or two.
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2017-05-19 19:18:35 -04:00 |
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Thomas Harte
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58efca835f
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Sought to add a further opcode.
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2017-05-18 22:53:43 -04:00 |
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Thomas Harte
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da6e520b91
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Merge branch 'master' into Z80
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2017-05-18 22:30:51 -04:00 |
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Thomas Harte
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9398b6c2c8
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Unable to differentiate, decided to map a Mac shift key to both Oric shifts.
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2017-05-18 22:25:59 -04:00 |
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Thomas Harte
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a3dafa9056
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Abbreviated uses of enumerations.
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2017-05-17 21:44:08 -04:00 |
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Thomas Harte
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64d6ee1be5
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Adjusted slightly to adapt to latest Swift warnings.
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2017-05-17 07:49:48 -04:00 |
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Thomas Harte
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1378ab7278
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Ensured initial program counter and stack pointer are correct for Zexall, fixed the Z80 to use a compile-time polymorphic call for bus access.
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2017-05-17 07:36:06 -04:00 |
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Thomas Harte
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87a021ec2d
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Made further attempt to get as fas as having the Z80 attempt to do something.
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2017-05-16 22:19:40 -04:00 |
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Thomas Harte
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189317b80c
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Added enough of a Z80 test machine to bridge up into Swift.
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2017-05-16 22:05:42 -04:00 |
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Thomas Harte
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4f0775cc7c
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Imported the Zexall.com tester, as a first thing to throw at the Z80 to be.
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2017-05-16 21:37:09 -04:00 |
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Thomas Harte
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7190f927b7
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Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
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2017-05-16 21:28:17 -04:00 |
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Thomas Harte
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d559d8b901
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Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
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2017-05-16 21:19:17 -04:00 |
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Thomas Harte
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df80c37adb
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Renamed TestMachine to TestMachine6502 since there's going to be multiple of them.
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2017-05-15 08:18:57 -04:00 |
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Thomas Harte
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0808e9b6fb
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Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.
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2017-05-14 22:08:15 -04:00 |
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Thomas Harte
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b81a2cc273
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First tentative steps towards adding a Z80 implementation.
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2017-05-14 17:46:41 -04:00 |
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Thomas Harte
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8e35e913bb
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Formally withdrew the 'load automatically' option for the Vic, having removed that option elsewhere.
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2017-05-14 16:59:24 -04:00 |
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