Thomas Harte
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fab6908129
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Corrects the all-RAM Z80 to declare that it needs the wait line to be implemented.
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2017-08-26 23:18:11 -04:00 |
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Thomas Harte
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57bfec285f
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Makes it optional whether the Z80 supports the wait line. If the wait line isn't in use, runtime costs are decreased because the optional wait cycles need not be iterated over.
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2017-08-26 23:08:57 -04:00 |
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Thomas Harte
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fa19e2d9c2
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Removes some detritus.
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2017-08-24 22:00:21 -04:00 |
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Thomas Harte
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95d360251d
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Makes all of PartialMachineCycle const, with the exception of the target of *value, since that's intended to be writeable by recipients.
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2017-08-24 21:32:33 -04:00 |
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Thomas Harte
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7af3de010e
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Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
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2017-08-23 22:25:31 -04:00 |
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Thomas Harte
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ee71be0e7e
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Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
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2017-08-21 21:56:42 -04:00 |
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Thomas Harte
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e1aded0d95
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Allows Z80 users to opt out of support for the bus request line. Which both now do.
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2017-08-21 20:43:12 -04:00 |
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Thomas Harte
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6315c22b80
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Removed repeated checking of bus_request_line_. It's now checked only after each outward perform_machine_cycle.
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2017-08-20 12:39:45 -04:00 |
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Thomas Harte
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42b5b66305
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Remove the 6502's use of runtime polymorphism in favour of ordinary templating.
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2017-08-16 11:56:52 -04:00 |
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Thomas Harte
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039811ce6a
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Switched the Z80 to being something a machine has, not something a machine is.
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2017-08-02 22:09:59 -04:00 |
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Thomas Harte
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4abd62e62b
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Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
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2017-07-27 22:05:29 -04:00 |
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Thomas Harte
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9ef232157b
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Revoked the operator bool() on WrappedInt as providing an indirect means for implicit but incorrect assignment to unwrapped ints. Got explicit about run_for intention and simplified HalfClockReceiver slightly by building a lossy and a flushing conversion to Cycles into HalfCycles. Adapted the all-RAM Z80 properly to return HalfCycles.
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2017-07-27 21:38:50 -04:00 |
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Thomas Harte
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8848ebbd4f
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Formalised set_interrupt_line's optional parameter as being a count of HalfCycles; corrected PartialMachineCycle.is_wait and effected the proper timing for counter reset on a ZX81.
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2017-07-27 21:10:14 -04:00 |
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Thomas Harte
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37950143fc
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Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
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2017-07-27 20:17:13 -04:00 |
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Thomas Harte
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60e374dca3
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Merge branch 'master' into Memptr
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2017-07-27 07:54:25 -04:00 |
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Thomas Harte
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8361756dc4
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Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
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2017-07-27 07:40:02 -04:00 |
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Thomas Harte
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847e49ccdf
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Corrected timestamp reporting by the all-RAM Z80.
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2017-07-26 19:47:39 -04:00 |
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Thomas Harte
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81a3899381
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Adjusted the Z80 formally to communicate in terms of half cycles rather than whole.
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2017-07-26 19:42:00 -04:00 |
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Thomas Harte
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9257a3f6d7
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Added test for 16-bit arithmetic, and fixed implementation.
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2017-07-26 19:04:52 -04:00 |
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Thomas Harte
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6ec4e4e3d7
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Merge branch 'master' into Memptr
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2017-07-25 23:01:34 -04:00 |
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Thomas Harte
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966b5e6372
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Adapted the Z80's perform_machine_cycle to return Cycles.
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2017-07-25 22:25:44 -04:00 |
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Thomas Harte
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279c369a1f
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Switched to Cycles as the result from the 6502 perform_bus_operation, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.
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2017-07-25 22:21:09 -04:00 |
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Thomas Harte
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75d67ee770
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Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
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2017-07-25 20:20:55 -04:00 |
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Thomas Harte
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a1e9a54765
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Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
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2017-07-25 20:09:13 -04:00 |
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Thomas Harte
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677ed463f0
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Updated comment per new method name.
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2017-07-24 21:19:49 -04:00 |
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Thomas Harte
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9bff787ee1
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Corrected for the new, non-integral type.
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2017-07-24 21:05:07 -04:00 |
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Thomas Harte
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b82bef95f3
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Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
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2017-07-24 20:10:05 -04:00 |
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Thomas Harte
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ace8e30818
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Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
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2017-07-23 22:21:39 -04:00 |
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Thomas Harte
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ec3aa06caf
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Removed dangling reference.
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2017-07-23 22:16:00 -04:00 |
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Thomas Harte
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ba088e5545
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Adapted the Z80 into a clock receiver, which also vends Cycles rather than a raw int within its PartialMachineCycle struct. The objective is to update it to vend HalfCycles within its struct, but I think I need to do some work on cycle/half-cycle arithmetic first.
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2017-07-23 22:15:04 -04:00 |
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Thomas Harte
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2ff157cf7a
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Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that.
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2017-07-22 22:17:29 -04:00 |
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Thomas Harte
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83628b285b
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Experimentally turned the 6502 into a clock receiver. No problem encountered.
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2017-07-22 21:52:21 -04:00 |
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Thomas Harte
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20a6bcc676
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Added tests for the various LD (nn), rr instructions and corrected implementation to pass.
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2017-07-22 11:39:13 -04:00 |
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Thomas Harte
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eaf313b0f6
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Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.
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2017-07-22 11:20:21 -04:00 |
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Thomas Harte
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d51b66c204
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Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.
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2017-07-21 23:01:35 -04:00 |
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Thomas Harte
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540a03f75c
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Exposed the memptr register.
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2017-07-21 22:31:42 -04:00 |
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Thomas Harte
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9b72c445a7
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Fixed indexing type.
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2017-07-21 21:19:46 -04:00 |
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Thomas Harte
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aec4fd066b
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I think I've definitively decided against this model of timing.
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2017-06-22 21:32:14 -04:00 |
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Thomas Harte
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95a6b0f85c
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Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
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2017-06-22 21:09:26 -04:00 |
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Thomas Harte
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b7c978e078
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Added getters for most of the input lines, and attempted to round out the ZX81's wait logic.
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2017-06-22 20:11:19 -04:00 |
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Thomas Harte
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f0398a6db8
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Added wait state hooks to the interrupt programs, and added an is_wait query on PartialMachineCycle.
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2017-06-22 20:07:47 -04:00 |
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Thomas Harte
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7eeac3b586
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Switched R back to incrementing after the refresh cycle. It had snuck to before by virtue of subdivision of the M1 cycle. Which shortened the ZX80 line time, breaking synchronisation.
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2017-06-21 21:11:00 -04:00 |
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Thomas Harte
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0e0ce379b4
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Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
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2017-06-21 20:38:08 -04:00 |
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Thomas Harte
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36e8a11505
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Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
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2017-06-21 20:32:08 -04:00 |
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Thomas Harte
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45f442ea63
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Corrected interrupt mode 2: was both failing properly to load the vector address, and failing to read from it.
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2017-06-21 19:08:48 -04:00 |
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Thomas Harte
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db743c90d8
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Had neglected to count refresh time in my interrupt programs. Corrected. Mode 0 timing test succeeds again. Only Mode 2 is now at fault.
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2017-06-21 18:58:44 -04:00 |
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Thomas Harte
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10cc94f581
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Attempted to fix interrupt response timing; ensured initial interrupt mode is one that won't jump beyond the interrupt response program table's length, and that the conditionals other than CALL definitely have no alternative program attached.
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2017-06-21 18:47:00 -04:00 |
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Thomas Harte
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108da64562
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Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
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2017-06-20 22:25:00 -04:00 |
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Thomas Harte
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f85b46286e
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Resolved the timing disparity between LD (HL),n and LD (IX+d), n, hopefully having come up with a convincing theory of timing for the latter.
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2017-06-20 22:20:58 -04:00 |
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Thomas Harte
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184b371649
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Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
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2017-06-20 21:48:50 -04:00 |
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