18 Commits

Author	SHA1	Message	Date
Thomas Harte	a3d37640aa	Switch include guards to #pragma once.	2024-01-16 23:34:46 -05:00
Thomas Harte	2b56b7be0d	Simplify namespace syntax.	2023-05-10 16:02:18 -05:00
Thomas Harte	4fc25fb798	Adds basic shift input.	2021-11-07 05:18:54 -08:00
Thomas Harte	ecfe68d70f	Introduce the principle that a Serial::Line can be two-wire — clock + data.	2021-11-06 16:54:20 -07:00
Thomas Harte	6d34432988	Starts to build in a serial line for input.	2021-11-04 18:54:28 -07:00
Thomas Harte	eb157f15f3	Adds index hole interrupt.	2021-10-09 04:08:59 -07:00
Thomas Harte	b4ec9d70da	Adds the CNT input.	2021-08-03 22:19:41 -04:00
Thomas Harte	0245b040b0	Splits TOD storage by model. ... TOD storage will probably end up being a full-on class.	2021-08-03 18:50:58 -04:00
Thomas Harte	460a6cb6fe	Attempts a more literal implementation.	2021-08-01 18:14:10 -04:00
Thomas Harte	759007ffc1	Attempts to route CIA interrupts.	2021-07-28 19:36:30 -04:00
Thomas Harte	c733a4dbf8	Beefs up interrupt awareness.	2021-07-23 21:58:52 -04:00
Thomas Harte	d898a43dff	Implements time-of-day counters, provisionally. ... Interrupts to do.	2021-07-23 21:24:07 -04:00
Thomas Harte	56b62a5e49	Adds a dummy interrupt control register.	2021-07-22 16:09:32 -04:00
Thomas Harte	a030d9935e	Adds port input.	2021-07-18 20:25:04 -04:00
Thomas Harte	c425dec4d5	Makes some attempt to get as far as the overlay being disabled.	2021-07-18 17:17:41 -04:00
Thomas Harte	67d53601d5	Latch and return data direction. ... Albeit with no port-handling effect yet.	2021-07-18 12:23:47 -04:00
Thomas Harte	48999c03a5	Adds concept of time, captured port handler.	2021-07-18 11:49:10 -04:00
Thomas Harte	377cc7bdcd	Start to introduce a 6526/8250.	2021-07-18 11:36:13 -04:00