Thomas Harte
4dd235f677
Adds supervisor/user to logged flags in trace mode.
2019-12-08 22:39:10 -05:00
Thomas Harte
407cc78c78
Extends to offer simpler 8-bit access handling.
2019-12-08 20:19:44 -05:00
Thomas Harte
b12136691a
Corrects comment.
2019-11-18 23:46:33 -05:00
Thomas Harte
db03b03276
Corrects [AND/OR/EOR].bw Dn, -(An) to decrement destination.
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It was previously doing a predecrement on the internal source address, which is unused. This fixes at least Dan Dare III and Silkworm.
2019-11-09 11:25:23 -05:00
Thomas Harte
6afefa107e
Resolves unused variable warning.
2019-11-05 23:18:25 -05:00
Thomas Harte
07582cee4a
BusGrant is a further signal I will need.
2019-11-03 21:10:42 -05:00
Thomas Harte
a67e0014a4
Fixes video base address and mono/colour monitor value.
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Now I see a GEM desktop. In blue.
2019-11-02 19:36:15 -04:00
Thomas Harte
c070f2100c
Attempts to regularise data bus access.
2019-11-01 23:01:06 -04:00
Thomas Harte
1c154131f9
Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.
2019-10-29 22:36:29 -04:00
Thomas Harte
ecc0cea5a1
Added a potential branch for the newer TOS memory map.
2019-10-26 16:52:06 -04:00
Thomas Harte
8a14f5d814
Updates to Xcode11 recommended project settings.
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The updated compiler also flagged a potential issue with CPU::Z80::Register not being a namespace re: 'Refresh' versus CPU::Z80::PartialMachineCycle. I don't entirely see it, but this fixes the problem.
I also finally figured out what the compiler was trying to tell me about ROMRequester.xib.
2019-09-22 12:13:56 -04:00
Thomas Harte
6a80832140
Moves timing of interrupt sampling into prefetch queue advancement.
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As per comment, that is definitely the only place it can occur; I don't know whether it always occurs there.
2019-08-04 21:06:34 -04:00
Thomas Harte
35b1a55c12
Corrects DIVS negative flag.
2019-08-04 20:36:33 -04:00
Thomas Harte
e3794c0c0e
Takes a second pass at DIVS timing, seeming to correct that side of things.
2019-08-04 20:33:43 -04:00
Thomas Harte
478f2533b5
Corrects 68000 address bus during interrupt acknowledge.
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All unused bits should be 1, not 0.
2019-08-03 15:38:36 -04:00
Thomas Harte
b7b62aa3f6
Resolves some type conversion warnings.
2019-07-26 23:20:40 -04:00
Thomas Harte
5769944918
Shrinks MicroOp struct size from 16 bytes to 4.
2019-07-25 10:14:36 -04:00
Thomas Harte
9ef1211d53
Adds missing header file.
2019-07-24 22:13:32 -04:00
Thomas Harte
f2ae04597f
Updates test case.
2019-07-24 22:07:17 -04:00
Thomas Harte
1327de1c82
Slims the Program struct down to 8 bytes total.
2019-07-24 22:02:50 -04:00
Thomas Harte
827c4e172a
Cuts a third from the Program struct.
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Observation: [source/destination]_address are always one of the address registers. So you can fit both within a single byte.
Net effect: around a 12% reduction in execution costs, given that this reduces the size of the instructions table from 3mb to 2mb.
2019-07-24 18:39:36 -04:00
Thomas Harte
c300bd17fa
Regularises as many source/destination sets as fit the current setter.
2019-07-24 18:22:44 -04:00
Thomas Harte
0187fd8eae
Hides all runtime Program member accesses behind macros.
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... and fixes unit tests.
2019-07-24 12:01:30 -04:00
Thomas Harte
4aca6c5ef8
Adds a note of admission here.
2019-07-23 23:03:15 -04:00
Thomas Harte
fa226bb1b9
Seeks to reduce enquiry costs.
2019-07-17 15:09:26 -04:00
Thomas Harte
cac97a9663
Devolves drive responsibility.
2019-07-10 22:39:56 -04:00
Thomas Harte
2ccb564a7b
Throws some extra logging into place, to test the IWM changeover.
2019-07-10 21:39:45 -04:00
Thomas Harte
ed4ddcfda8
Reduces call/return overhead on Microcycle methods.
2019-07-09 19:55:30 -04:00
Thomas Harte
69b94719a1
Switches to faster bit count logic.
2019-07-09 18:41:20 -04:00
Thomas Harte
5078f6fb5c
Marginally reduces MOVE heft.
2019-07-09 18:07:11 -04:00
Thomas Harte
94457d81b6
Eliminates redundant and integer-size-troubling AND on ASL.
2019-07-08 18:33:50 -04:00
Thomas Harte
fb352a8d40
Ensures assert is completely excluded if NDEBUG.
2019-07-08 18:00:37 -04:00
Thomas Harte
b9c2c42bc0
Switches drives to using floats for time counting.
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Hopefully to eliminate a lot of unnecessary `Time` work; inaccuracies should still be within tolerable range.
2019-07-02 15:43:03 -04:00
Thomas Harte
c4cbe9476c
Corrects EA selection logic, fixing MOVEP.
2019-07-02 13:54:21 -04:00
Thomas Harte
0a67cc3dab
Goes nuclear on ROXL and ROXR.
2019-07-01 23:05:48 -04:00
Thomas Harte
726e07ed5b
Corrects ASL overflow flag.
2019-07-01 19:46:58 -04:00
Thomas Harte
11d8f765b2
Corrects divide-by-zero exception length, enables all other DIVS checks.
2019-07-01 15:46:04 -04:00
Thomas Harte
514e57b3e9
Corrects DIVU timing and flags, improves DIVS.
2019-07-01 14:24:32 -04:00
Thomas Harte
d8fb6fb951
Corrects MULU timing.
2019-06-30 22:40:10 -04:00
Thomas Harte
255f0d4b2a
Corrects MULS timing.
2019-06-30 22:33:54 -04:00
Thomas Harte
8d0cd356fd
Corrects TRAP, TRAPV and CHK timing.
2019-06-29 21:25:22 -04:00
Thomas Harte
17666bc059
Corrects CHK flags.
2019-06-28 19:48:53 -04:00
Thomas Harte
241d29ff7c
Imports SBCD and NBCD tests, and fixes corresponding operation.
2019-06-28 19:39:08 -04:00
Thomas Harte
c5039a4719
Imports ANDI, ORI and EORI to SR tests.
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Hence corrects supervisor/user privileges for SR/CCR.
2019-06-28 15:05:46 -04:00
Thomas Harte
6c588a1510
Makes some further random swings at tracking the startup procedure.
2019-06-28 13:03:47 -04:00
Thomas Harte
d81053ea38
Invents some additional PEA tests, and further fixes PEA.
2019-06-27 17:59:03 -04:00
Thomas Harte
8d39c3bc98
Takes a shot at fixing PEA for A7-relative addresses.
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Unit tests required. Tomorrow.
2019-06-26 23:24:54 -04:00
Thomas Harte
c0591090f5
Imports DIVU tests.
2019-06-26 22:25:48 -04:00
Thomas Harte
538aecb46e
Imports CMP tests, and fixes CMP.l timing.
2019-06-26 22:02:04 -04:00
Thomas Harte
dbdbea85c2
Imports CMPA tests, and fixes CMPA.w.
2019-06-26 21:42:48 -04:00
