Thomas Harte
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5db6a937cb
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Have TRAP and TRAPV push the next instruction address to the stack.
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2022-05-25 11:47:21 -04:00 |
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Thomas Harte
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9709b9b1b1
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Standard exceptions don't raise the interrupt level.
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2022-05-25 11:37:39 -04:00 |
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Thomas Harte
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5872e0ea4a
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Resolve MOVE.l xx, -(An) write target.
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2022-05-25 08:15:18 -04:00 |
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Thomas Harte
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f43d27541b
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Avoid attempt to establish operand flags for undefined opcodes.
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2022-05-24 15:53:12 -04:00 |
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Thomas Harte
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0f7cb2fa5a
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Attempt to honour the trace flag.
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2022-05-24 15:47:47 -04:00 |
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Thomas Harte
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01e93ba916
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Make an attempt at bus/address error.
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2022-05-24 15:42:50 -04:00 |
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Thomas Harte
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780954f27b
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Add TRAP, TRAPV.
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2022-05-24 15:14:46 -04:00 |
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Thomas Harte
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6f048de973
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Pull unrecognised instruction handling into the usual switch table.
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2022-05-24 12:42:34 -04:00 |
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Thomas Harte
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0dfaa7d9cf
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Interrupt fixes: supply proper address, raise level, fetch from vector.
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2022-05-24 12:16:06 -04:00 |
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Thomas Harte
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eab720f6ea
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Ensure proper transition from unrecognised instructions.
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2022-05-24 12:16:00 -04:00 |
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Thomas Harte
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a7e8aef9d3
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Add MOVEA, be slightly more careful about next_operand_.
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2022-05-24 11:30:09 -04:00 |
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Thomas Harte
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df54f1f1b7
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Update TODO.
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2022-05-24 11:06:05 -04:00 |
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Thomas Harte
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9e3c2b68d7
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Eliminate potential future implicit conversion warnings.
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2022-05-24 11:05:24 -04:00 |
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Thomas Harte
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3349bcaaed
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Attempt interrupt support.
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2022-05-24 10:53:59 -04:00 |
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Thomas Harte
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3a4fb81242
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Add a dummy STOP state.
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2022-05-24 10:25:40 -04:00 |
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Thomas Harte
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1df3ad0671
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Ensure TAS responds to VPA, BERR.
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2022-05-24 09:17:58 -04:00 |
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Thomas Harte
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523cdd859b
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Add bus and address error, and VPA checks.
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2022-05-24 09:08:31 -04:00 |
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Thomas Harte
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9cac4ca317
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Add MOVE to/from USP.
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2022-05-23 20:42:41 -04:00 |
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Thomas Harte
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34e5f39571
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Ensure that running exactly up to a boundary gives the bus handler the next microcycle to contemplate.
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2022-05-23 15:11:33 -04:00 |
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Thomas Harte
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e0a279344c
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Codify the existence of special cases, implement NOP and RESET.
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2022-05-23 15:09:46 -04:00 |
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Thomas Harte
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c1837af84a
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Add notes to self on work remaining.
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2022-05-23 11:02:31 -04:00 |
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Thomas Harte
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a87f6a28c9
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Fix LINK A7.
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2022-05-23 10:43:17 -04:00 |
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Thomas Harte
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98325325b1
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Fix UNLINK A7.
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2022-05-23 10:27:44 -04:00 |
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Thomas Harte
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26bf66e3f8
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Fix shifts and rolls.
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2022-05-23 10:09:46 -04:00 |
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Thomas Harte
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c6b3281274
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Attempt the shifts and rolls.
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2022-05-23 09:29:19 -04:00 |
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Thomas Harte
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1e8adc2bd9
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Fix MOVEP to R.
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2022-05-23 09:00:37 -04:00 |
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Thomas Harte
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c73021cf3c
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Implement MOVE.
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2022-05-23 08:46:06 -04:00 |
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Thomas Harte
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1b3acf9cd8
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Eliminate assumption.
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2022-05-23 08:18:37 -04:00 |
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Thomas Harte
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c8ede400eb
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Fix RTE.
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2022-05-22 21:17:28 -04:00 |
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Thomas Harte
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269263eecf
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Implement RTE, RTS, RTR.
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2022-05-22 21:16:38 -04:00 |
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Thomas Harte
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faef5633f8
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Ensure MOVE from SR has an effective address to write to.
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2022-05-22 20:52:00 -04:00 |
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Thomas Harte
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7d1f1a3175
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Implement MOVE [to/from] [CCR/SR].
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2022-05-22 19:45:22 -04:00 |
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Thomas Harte
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4e34727195
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Fully implement TAS.
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2022-05-22 16:14:03 -04:00 |
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Thomas Harte
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1dd6ed6ae3
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Implement TAS Dn, with detour for other TASes.
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2022-05-22 16:08:30 -04:00 |
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Thomas Harte
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3b68b9a83b
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Implement PEA.
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2022-05-22 11:27:38 -04:00 |
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Thomas Harte
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4279ce87ea
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Implement LEA.
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2022-05-22 08:29:12 -04:00 |
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Thomas Harte
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3c1c4f89e9
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Add MULU/S functionality, though not timing.
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2022-05-22 08:02:32 -04:00 |
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Thomas Harte
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4a6512f5d5
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Reduce dispatch boilerplate.
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2022-05-22 07:39:16 -04:00 |
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Thomas Harte
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284f23c6ea
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Implement JMP.
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2022-05-22 07:16:38 -04:00 |
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Thomas Harte
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11a9a5c126
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Use common macros for the two forms of Perform.
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2022-05-22 07:08:14 -04:00 |
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Thomas Harte
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4993801741
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Add missing prefetch to BSET, BCHG, BCLR.
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2022-05-21 21:05:05 -04:00 |
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Thomas Harte
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4b35899a12
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Bcc: properly establish offset.
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2022-05-21 20:59:34 -04:00 |
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Thomas Harte
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1304e930eb
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DBcc is two-operand.
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2022-05-21 20:06:03 -04:00 |
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Thomas Harte
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94288d5a94
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Excludes DBcc from standard operand fetch.
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2022-05-21 19:53:28 -04:00 |
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Thomas Harte
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3811ab1b82
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Fix the two 8bit-with-displacement effective address Calc steps.
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2022-05-21 16:20:01 -04:00 |
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Thomas Harte
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f97d2a0eb9
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Add DIVU/DIVS, at least as far as getting the correct numeric result.
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2022-05-21 15:56:09 -04:00 |
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Thomas Harte
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2258434326
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Ensure proper return addresses are calculated for JSR.
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2022-05-21 14:28:44 -04:00 |
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Thomas Harte
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e46a3c4046
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Implement JSR.
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2022-05-21 10:29:36 -04:00 |
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Thomas Harte
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0e4cfde657
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Fix MOVEM predec.
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2022-05-21 08:17:39 -04:00 |
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Thomas Harte
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4bd9c36922
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Fix postincrement mode.
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2022-05-20 21:01:23 -04:00 |
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