Thomas Harte
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a6810fc3ef
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Removed some minor duplicity and ensured that hsync/NMI ends on the nominated cycle, not one afterwards.
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2017-06-21 21:44:42 -04:00 |
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Thomas Harte
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15f6c51062
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Added the most trivial implementation of the ZX81 wait line.
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2017-06-21 21:28:14 -04:00 |
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Thomas Harte
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5e21c706f3
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Merge pull request #132 from TomHarte/MachineCycles
Subdivides the Z80's machine cycles
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2017-06-21 21:19:48 -04:00 |
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Thomas Harte
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e1355d4b62
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Restored proper video output.
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2017-06-21 21:18:09 -04:00 |
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Thomas Harte
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7eeac3b586
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Switched R back to incrementing after the refresh cycle. It had snuck to before by virtue of subdivision of the M1 cycle. Which shortened the ZX80 line time, breaking synchronisation.
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2017-06-21 21:11:00 -04:00 |
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Thomas Harte
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4bf13610ce
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Reinstated interrupts by moving the refresh test back into the refresh cycle.
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2017-06-21 21:03:39 -04:00 |
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Thomas Harte
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0e0ce379b4
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Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
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2017-06-21 20:38:08 -04:00 |
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Thomas Harte
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36e8a11505
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Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
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2017-06-21 20:32:08 -04:00 |
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Thomas Harte
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45f442ea63
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Corrected interrupt mode 2: was both failing properly to load the vector address, and failing to read from it.
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2017-06-21 19:08:48 -04:00 |
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Thomas Harte
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db743c90d8
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Had neglected to count refresh time in my interrupt programs. Corrected. Mode 0 timing test succeeds again. Only Mode 2 is now at fault.
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2017-06-21 18:58:44 -04:00 |
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Thomas Harte
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10cc94f581
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Attempted to fix interrupt response timing; ensured initial interrupt mode is one that won't jump beyond the interrupt response program table's length, and that the conditionals other than CALL definitely have no alternative program attached.
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2017-06-21 18:47:00 -04:00 |
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Thomas Harte
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108da64562
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Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
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2017-06-20 22:25:00 -04:00 |
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Thomas Harte
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f85b46286e
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Resolved the timing disparity between LD (HL),n and LD (IX+d), n, hopefully having come up with a convincing theory of timing for the latter.
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2017-06-20 22:20:58 -04:00 |
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Thomas Harte
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184b371649
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Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
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2017-06-20 21:48:50 -04:00 |
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Thomas Harte
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b0375bb037
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Fixed the three LD rr, (nn) operations. Back down to four FUSE failures.
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2017-06-20 21:32:23 -04:00 |
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Thomas Harte
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48942848e7
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Fixed (Ix+d) read timing. I've put an extra wait cycle into the read, so no need to extend the refresh.
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2017-06-20 21:15:56 -04:00 |
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Thomas Harte
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27ac342928
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Corrected conditional call timing, and its test.
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2017-06-20 20:57:23 -04:00 |
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Thomas Harte
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25aba16ef8
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Quickly checking the FUSE tests, corrected a handful of instances where PC should be modified but isn't, correcting around 800 new failures.
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2017-06-19 22:20:23 -04:00 |
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Thomas Harte
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a0d0f383c8
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Corrected unconditional CALL timing. Conditional's going to require more work because once the wait state is put into the right place, it breaks the assumption under which the Z80 handles conditions — that they're either do something or else do nothing. So that can wait a day.
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2017-06-19 22:07:36 -04:00 |
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Thomas Harte
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6752f165db
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Added failing tests for both kinds of CALL.
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2017-06-19 22:03:29 -04:00 |
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Thomas Harte
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e05076b258
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Added tests for everything except CALL. All passing.
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2017-06-19 22:00:04 -04:00 |
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Thomas Harte
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fadbfdf801
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Added DJNZ test.
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2017-06-19 21:31:56 -04:00 |
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Thomas Harte
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cb277b8d1e
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Added JP and JR tests.
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2017-06-19 21:27:23 -04:00 |
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Thomas Harte
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234f14dbbe
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Tests were at fault; all passing now.
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2017-06-19 21:14:40 -04:00 |
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Thomas Harte
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99ede3a9ef
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BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).
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2017-06-19 21:04:14 -04:00 |
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Thomas Harte
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378233f53d
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Extended to BITs and SETs, accruing three new failures.
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2017-06-19 21:01:30 -04:00 |
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Thomas Harte
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f903408980
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Caught up on comments.
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2017-06-19 20:53:22 -04:00 |
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Thomas Harte
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cc8f316941
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Resolved read-modify-write (IX+d) timing, and therefore RLC (IX+d).
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2017-06-19 20:51:28 -04:00 |
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Thomas Harte
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b684254908
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Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
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2017-06-19 20:33:34 -04:00 |
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Thomas Harte
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351d90ca55
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Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.
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2017-06-19 20:04:55 -04:00 |
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Thomas Harte
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23177df26a
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Added various tests of the basic ALU ops.
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2017-06-19 19:53:26 -04:00 |
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Thomas Harte
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ba15371948
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Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
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2017-06-19 19:47:00 -04:00 |
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Thomas Harte
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73dbaebbc1
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Fixed timing of EX (SP), HL/IX.
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2017-06-19 19:25:53 -04:00 |
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Thomas Harte
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8d60734737
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Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.
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2017-06-19 19:17:54 -04:00 |
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Thomas Harte
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002098d496
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The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.
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2017-06-19 07:45:41 -04:00 |
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Thomas Harte
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e3244eb68e
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Rephrased internal operation machine cycles as having only an end. So they're now easy to count. Hence the test machine spots them, and a couple more of the current timing subset passes.
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2017-06-19 07:39:46 -04:00 |
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Thomas Harte
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85c6fb1430
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Explained refresh cycles to the all-RAM Z80.
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2017-06-19 07:36:11 -04:00 |
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Thomas Harte
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54e4643396
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Corrected non-default refresh cycle lengths. Reduces failures of the currently-tested timing subset from 10 to 4.
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2017-06-19 07:34:23 -04:00 |
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Thomas Harte
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85c5c4405a
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Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
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2017-06-19 07:30:01 -04:00 |
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Thomas Harte
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d668879ba6
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Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
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2017-06-18 22:03:13 -04:00 |
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Thomas Harte
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cb140aa06e
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Managed to navigate back to building.
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2017-06-18 21:00:44 -04:00 |
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Thomas Harte
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6a769d3953
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Finally dipped below the 20 error threshold that the compiler tops out at.
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2017-06-18 20:34:46 -04:00 |
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Thomas Harte
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3be8ffd826
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Some correct timings have gone out the window for now, but only the final quarter of the base page now contains compiler errors.
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2017-06-18 20:31:12 -04:00 |
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Thomas Harte
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bb910e14a4
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Dealt with the CB page.
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2017-06-18 18:01:33 -04:00 |
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Thomas Harte
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69ebbe019a
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Completed ED page conversion. Rolling onwards...
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2017-06-18 17:56:48 -04:00 |
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Thomas Harte
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0d39672d32
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Fixing typos here and there, persuaded the first half of the ED table to compile.
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2017-06-18 17:48:54 -04:00 |
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Thomas Harte
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0d1231980a
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Advanced to getting specific warnings in the ed-page table. So that's progress.
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2017-06-18 17:25:15 -04:00 |
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Thomas Harte
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82a015892b
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Started adapting to the newly-segmented world.
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2017-06-18 17:18:01 -04:00 |
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Thomas Harte
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194b7f60c5
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Rephrased to allow non-conditional waits; expanded macros to cover all permitted lengths of read and write.
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2017-06-18 17:08:50 -04:00 |
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Thomas Harte
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ebc7356db5
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Reformulated the machine cycle slightly to support posting operation plus phase, thereby exposing the segue points at which waits might be inserted. So: to stick to the rule that CPUs expose the minimum amount of information sufficient completely to reconstruct bus activity. This breaks the Z80 for now.
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2017-06-18 12:21:27 -04:00 |
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