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Author SHA1 Message Date
Thomas Harte
abe55fe950 Adds Timer 1 toggling of PB7. 2019-06-03 15:39:20 -04:00
Thomas Harte
4d4ddded6d Fixes register-relative JMP and JSR. 2019-06-03 15:29:50 -04:00
Thomas Harte
1328708a70 Switches to testing against the Mac Plus ROM. 
Immediately uncovering an issue with JMP.
 2019-06-03 14:54:18 -04:00
Thomas Harte
85298319fa Expands towards supporting multiple Macintosh models. 
To provide another variable to help with bug isolation.
 2019-06-03 14:50:36 -04:00
Thomas Harte
881feb1bd3 Adds preliminary parsing of the Disk Copy 4.2 format. 2019-06-02 13:39:25 -04:00
Thomas Harte
3e9fa63799 Adds a receiver for drive-motor control bytes. 
My new belief is that I'm either reading the buffer from the wrong place, or the 68000 isn't filling it for some reason.
 2019-06-01 19:31:32 -04:00
Thomas Harte
da2b190288 Stores expected bit length. 2019-06-01 19:08:29 -04:00
Thomas Harte
48d837c636 Attempts to respond more sensibly to various queries. 
Including adding a 1-second delay on motor off.
 2019-06-01 18:43:47 -04:00
Thomas Harte
983407896c Ensures consistent audio pipeline. 2019-06-01 17:29:57 -04:00
Thomas Harte
5c08bb810e In theory provides a full implementation of audio. 
Albeit seemingly ineffective.
 2019-06-01 15:44:29 -04:00
Thomas Harte
17635da812 Pushes Mac audio further towards being able to function. 2019-06-01 15:18:27 -04:00
Thomas Harte
6d985866ee All proper inputs are now provided to the audio generator. 
Hopefully. The next job is to generate audio. If that sounds correct, then the disk motor speed question can be tackled.
 2019-06-01 15:03:15 -04:00
Thomas Harte
723137c0d4 With some time additions to the 6522, starts wiring in Macintosh audio. 
The audio buffer is also the disk motor buffer, so this is preparatory to further disk work.
 2019-06-01 14:39:40 -04:00
Thomas Harte
938928865d Merge branch 'master' into Mac128k 2019-05-30 22:29:56 -04:00
Thomas Harte
d80b0cbf90
Merge pull request #622 from TomHarte/SConstructUTF 
Adds recommended fix for 0xc3 in position 12 error.
 2019-05-30 22:25:57 -04:00
Thomas Harte
e88ef30ce6 Adds recommended fix for 0xc3 in position 12 error. 2019-05-30 22:20:15 -04:00
Thomas Harte
4197c6f149 Attempts to make some further semantic sense of the various IWM controls. 2019-05-30 22:17:49 -04:00
Thomas Harte
035f07877c Reduces conversions to vector. 2019-05-30 12:08:35 -04:00
Thomas Harte
4632be4fe5 Wires up the final IWM signal, SEL, preparatory to an implementation. 2019-05-30 12:08:00 -04:00
Thomas Harte
b3d2b4cd37 Fixes the interrupt return address. 2019-05-29 20:27:46 -04:00
Thomas Harte
c86fe9ada9 Ensures replace_write_values works in release builds. 2019-05-29 19:00:53 -04:00
Thomas Harte
ecf93b7822 Eliminates some type conversion warnings. 2019-05-29 14:56:50 -04:00
Thomas Harte
541b75ee6e Further fixes PEA, and OR/AND/EOR Dn, (An). 2019-05-29 14:37:15 -04:00
Thomas Harte
77b08febdb Corrects PEA and adds an additional debugging aid. 2019-05-29 12:47:17 -04:00
Thomas Harte
fcda376f33 Removes three further type conversion warnings. 2019-05-28 21:56:49 -04:00
Thomas Harte
0848fc7e03 Ensures the Mac uses auto vectored interrupts. 2019-05-28 16:24:41 -04:00
Thomas Harte
3bb8d6717f Ensures A7 is correct at end of an UNLINK. 2019-05-28 16:02:42 -04:00
Thomas Harte
5e2496d59c Simplifies and corrects MOVE logic. 2019-05-28 15:17:03 -04:00
Thomas Harte
c52da9d802 Adds some logging preparatory to a MOVE change. 2019-05-28 15:05:42 -04:00
Thomas Harte
1d3dde32f2 Ensures final byte of data can be accessed. 2019-05-09 07:24:26 -04:00
Thomas Harte
0b999ce0e4 Attempts to fix register-relative JSRs. 2019-05-09 06:43:07 -04:00
Thomas Harte
b04bd7069d Corrects Scc and DBcc (xxx).l and (xxx).w. 2019-05-09 06:28:55 -04:00
Thomas Harte
249b0fbb32 Corrects PC on stack after an illegal instruction. 
Also fixed LOG_TRACE functionality.
 2019-05-08 22:36:25 -04:00
Thomas Harte
41740fb45e Implements video position feedback. 
At a substantial performance cost for now, but I'll worry about that once things are working.
 2019-05-08 16:54:19 -04:00
Thomas Harte
0ad88508f7 Removes ROM mirroring above $600000. 2019-05-08 15:07:03 -04:00
Thomas Harte
8293b18278 Adds a TODO on what I think might be an incorrect implementation? 2019-05-08 15:06:40 -04:00
Thomas Harte
2ba0364850 Adds the shift register interrupt. 2019-05-08 15:02:07 -04:00
Thomas Harte
8b72043f33 Ensures no uninitialised variables. 2019-05-08 14:54:54 -04:00
Thomas Harte
2e7bc0b98a Attempts the shift register. 2019-05-08 14:54:40 -04:00
Thomas Harte
f0f9722ca6 Takes a first crack at the keyboard's serial protocol. 
Albeit that without a working shift register in the VIA, this shouldn't really work yet.
 2019-05-08 14:20:28 -04:00
Thomas Harte
b5ef88902b Edges further towards a functioning keyboard. 2019-05-08 13:58:52 -04:00
Thomas Harte
8278809383 Attempts to get more rigorous on communicating outward control line changes. 2019-05-08 13:33:22 -04:00
Thomas Harte
4367459cf2 Takes a first go at handshake and pulse modes. 2019-05-08 12:48:29 -04:00
Thomas Harte
254132b83d Eliminates 6522Base in pursuit of working handshake modes. 
Specifically: this means that the places from which the BusHandler may be called are more numerous.
 2019-05-08 12:35:17 -04:00
Thomas Harte
7b466e6d0a Begins work on a functioning keyboard. 2019-05-08 12:34:26 -04:00
Thomas Harte
7e6d4f5a3e Adds emulation of the real-time clock. 2019-05-08 00:12:19 -04:00
Thomas Harte
ce099a297a Eliminates RAM writes in ROM area. 
I no longer think that logic is correct.
 2019-05-07 17:16:22 -04:00
Thomas Harte
949c848815 Broadens address decoding. 
To no obvious change in output.
 2019-05-06 22:57:29 -04:00
Thomas Harte
9bf9b9ea8c Ensures unmapped peripherals return a consistent value. 2019-05-06 21:32:10 -04:00
Thomas Harte
d8ed8b66f3 Improves carry/extend for ROXL and ROXR. 2019-05-06 21:14:16 -04:00