296 Commits

Author	SHA1	Message	Date
Thomas Harte	bdcab447f9	Add a further accessor.	2021-06-27 16:27:26 -04:00
Thomas Harte	d80f03e369	Corrects longstanding deviation from naming convention.	2021-04-25 14:11:36 -04:00
Thomas Harte	e7a9ae18a1	Introduce further default state.	2021-04-24 23:18:00 -04:00
Thomas Harte	77fcf52d27	Purely style: remove some redundant nullptrs.	2021-04-19 18:53:00 -04:00
Thomas Harte	79c2bc1fd7	Put the program counter on the bus during interrupt acknowledge.	2021-04-19 18:43:50 -04:00
Thomas Harte	7017324d60	r_step is obsolete now that I know that [DD/FD]CB don't have a refresh cycle.	2021-04-13 22:17:30 -04:00
Thomas Harte	deb5d69ac7	Consolidates macros.	2021-04-13 22:11:28 -04:00
Thomas Harte	5998f3b35b	Corrects LD[I/D/IR/DR] timing. ... Macro cleanup to come.	2021-04-13 20:00:18 -04:00
Thomas Harte	869567fdd9	Corrects EX (SP), HL breakdown.	2021-04-13 19:45:48 -04:00
Thomas Harte	b42780173a	Establishes that there really is no Read4 and Read4Pre distinction. ... Will finish these unit tests, then clean up.	2021-04-12 20:54:10 -04:00
Thomas Harte	947de2d54a	Switches five-cycle read to a post hoc pause.	2021-04-12 17:17:08 -04:00
Thomas Harte	e82367def3	Switches to test-conformant behaviour for (IX/IY+n) opcode fetches.	2021-04-11 23:01:00 -04:00
Thomas Harte	9cde7c12ba	Shifts responsibility for refresh into the fetch-decode-execute sequence.	2021-04-11 22:50:24 -04:00
Thomas Harte	015556cc91	Switch (ii+n) to Read4Pre.	2021-04-11 10:26:14 -04:00
Thomas Harte	b397059d5e	Moves read time in Read4Pre.	2021-04-10 17:54:20 -04:00
Thomas Harte	e0736435f8	Makes assumption that the address bus just holds its value during an internal operation.	2021-04-10 12:00:53 -04:00
Thomas Harte	eacffa49f5	Exposes IR during 'internal' operations.	2021-04-08 22:22:26 -04:00
Thomas Harte	29cf80339a	Corrects too-short buffer.	2021-04-08 22:15:03 -04:00
Thomas Harte	57a7e0834f	Corrects sampling of MREQ.	2021-04-08 19:21:35 -04:00
Thomas Harte	25b8c4c062	Provide clearer failure case.	2021-04-03 21:04:44 -04:00
Thomas Harte	1be88a5308	Remove first draft.	2021-04-02 07:39:22 -04:00
Thomas Harte	294280a94e	Spells out everything except interrupt acknowledge.	2021-04-02 07:38:06 -04:00
Thomas Harte	32aebfebe0	Starts spelling out meaning of the Z80's partial machine cycles.	2021-04-02 07:37:56 -04:00
Thomas Harte	76299a2add	Include AF' in Z80 state.	2021-03-29 22:58:52 -04:00
Thomas Harte	8641494809	Resolve various test-case warnings.	2020-09-27 15:10:29 -04:00
Thomas Harte	945a9da94f	Adds further [[fallthrough]]s.	2020-06-19 23:44:20 -04:00
Thomas Harte	2477752fa4	Adds further [[fallthrough]] attributes.	2020-06-19 23:36:51 -04:00
Thomas Harte	267006782f	Starts to add Qt target; resolves many build warnings.	2020-05-30 00:37:06 -04:00
Thomas Harte	512a52e88d	Increases const correctness, marks some additional constructors as constexpr, switches std::atomic construction style.	2020-05-20 23:34:26 -04:00
Thomas Harte	8b76d4007e	Starts adding State for the 68000.	2020-05-14 22:46:40 -04:00
Thomas Harte	c5b746543b	Factors the half mask into steps count.	2020-05-14 00:09:01 -04:00
Thomas Harte	11d936331d	Attempts to preserve scheduled_program_counter_.	2020-05-13 23:58:04 -04:00
Thomas Harte	3709aa7555	Edges almost up to an initially complete implementation.	2020-05-13 22:04:04 -04:00
Thomas Harte	7c9d9ee048	Adds basic Z80 state.	2020-05-13 20:15:22 -04:00
Thomas Harte	25996ce180	Further doubles down on construction syntax for type conversions.	2020-05-09 23:00:39 -04:00
Thomas Harte	b971e2a42c	Adds get_is_resetting to the Z80, eliminating the CPC's custom version.	2020-02-29 19:58:25 -05:00
Thomas Harte	01faffd5bf	Corrects memptr behaviour of OTIR/OTDR and INIR/INDR. ... This seemingly perfects memptr.	2020-02-27 20:55:43 -05:00
Thomas Harte	26de5be07c	Corrects memptr behaviour of LDIR/LDDR and CPIR/CPDR.	2020-02-27 20:44:53 -05:00
Thomas Harte	87474d5916	Corrects memptr behaviour of OUT (C), 0.	2020-02-27 20:38:27 -05:00
Thomas Harte	06163165d9	Corrects memptr effect of LD rr, (nn).	2020-02-26 22:22:54 -05:00
Thomas Harte	ec82c075be	Fixes memptr for IN C, (C).	2020-02-26 22:19:37 -05:00
Thomas Harte	3b0df172a7	Corrects memptr behaviour of JP nn.	2020-02-26 22:02:15 -05:00
Thomas Harte	7058dbc3cc	Corrects memptr for LD HL, (nn).	2020-02-26 21:54:49 -05:00
Thomas Harte	b64de89d2d	Corrects JR memptrs.	2020-02-26 21:47:34 -05:00
Thomas Harte	8878396339	Corrects DJNZ memptr behaviour.	2020-02-26 21:42:31 -05:00
Thomas Harte	3097c4ccae	Improves MEMPTR testing and some results.	2020-02-24 23:32:18 -05:00
Thomas Harte	7959d243f6	Adds single-stepping. Of a kind.	2020-02-24 23:31:42 -05:00
Thomas Harte	79dd402bc8	Consolidates different test port input selection.	2020-02-23 16:12:28 -05:00
Thomas Harte	3f3229851b	Implements MEMPTR for IN.	2020-02-23 00:32:33 -05:00
Thomas Harte	1c154131f9	Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.	2019-10-29 22:36:29 -04:00